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| tda5250 d2 ask/fsk 868mhz wireless transceiver data sheet, version 1.7, 2007-02-26 wireless components never stop thinking.
edition 2007-02-26 published by infineon technologies ag, am campeon 1-12, d-85579 neubiberg, germany ? infineon technologies ag 3/7/07. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. wireless components tda5250 d2 ask/fsk 868mhz wireless transceiver data sheet, version 1.7, 2007-02-26 never stop thinking. data sheet revision history: 2007-02-26 tda5250 d2 previous version: v1.6 as of july 2002 page subjects (major changes since last revision) 5 indication of the ordering code 5, 10 correction of the package name 79 indication of the esd-integrity values for questions on technology, deliver y and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4 c, slicofi ? are registered trademarks of infineon technologies ag. ace?, asm?, asp?, potswire?, quadfalc?, scout? are trademarks of infineon technologies ag. controller area network (can): license of robert bosch gmbh data sheet 5 2007-02-26 type ordering code package tda5250 d2 sp000012956 tda5250 d2 version 1.7 data sheet 6 2007-02-26 page table of contents 1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.1 power amplifier (pa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.2 low noise amplifier (lna) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.3 downconverter 1 st mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.4 downconverter 2 nd i/q mixers . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.5 pll synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4.6 i/q filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4.7 i/q limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4.8 fsk demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.9 data filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.10 data slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.11 peak detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.12 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.13 bandgap reference circuitry & powerdown . . . . . . . . . . . . . . . 22 2.4.14 timing and data control unit . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4.15 bus interface and register definition . . . . . . . . . . . . . . . . . . . . 24 2.4.16 wakeup logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.17 data valid detection, data pin . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.18 sequence timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.19 clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.20 rssi and supply voltage measurement . . . . . . . . . . . . . . . . . . 37 3 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1 lna and pa matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1.1 rx/tx switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switch in rx-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switch in tda5250 d2 version 1.7 data sheet 7 2007-02-26 page table of contents tx-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1.4 power-amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.2.1 synthesizer frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2.2 transmit/receive ask/fsk frequency assignment . . . . . . . . . 53 3.2.3 parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.2.4 calculation of the external capacitors . . . . . . . . . . . . . . . . . . . . 57 3.2.5 fsk-switch modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.6 finetuning and fsk modulation relevant registers . . . . . . . . . . 58 3.2.7 chip and system tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3 iq-filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4 data filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.5 limiter and rssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.6 data slicer - slicing level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.6.1 rc integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.6.2 peak detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.6.3 peak detector - analog output signal . . . . . . . . . . . . . . . . . . . . 67 3.6.4 peak detector ? power down mode . . . . . . . . . . . . . . . . . . . . . 67 3.7 data valid detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.7.1 frequency window for data rate detection . . . . . . . . . . . . . . . 70 3.7.2 rssi threshold voltage - rf input power . . . . . . . . . . . . . . . . . 71 3.8 calculation of on_time and off_time . . . . . . . . . . . . . . . . . . . 71 3.9 example for self polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.10 sensitivity measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.10.1 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.10.2 sensitivity depending on the ambient temperature . . . . . . . . . 75 3.10.3 ber performance depending on supply voltage . . . . . . . . . . . 76 3.10.4 datarates and sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.10.5 sensitivity at frequency offset . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.11 default setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.4 digital characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 tda5250 d2 version 1.7 data sheet 8 2007-02-26 page table of contents 4.2 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.3 test board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.4 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 tda5250 d2 version 1.7 product description data sheet 9 2007-02-26 1 product description 1.1 overview the ic is a low power consumption single chip fsk/ask transceiver for the frequency band 868- 870 mhz. the ic combines a very high level of integration and minimum external part count. the device contains a low noise amplifier (lna), a double balanced mixer, a fully integrated vco, a pll synthesizer, a crystal oscillator with fsk modulator, a limiter with rssi generator, an fsk demodulator, a data filter, a data comparator (slicer), a positive and a negative data peak detector, a highly efficient power amplifier and a complex digital timing and control unit with i 2 c/3-wire microcontroller interface. additionally there is a power down feature to save battery power. the transmit section uses direct ask modulation by switching the power amplifier, and crystal oscillator detuning for fsk modulation. the necessary detuning load capacitors are external. the capacitors for fine tuning are integrated. the receive section is using a novel single-conversion/ direct-conversion scheme that is combining the advantages of both receive topologies. the if is contained on the chip, no rf channel filters are necessary as the channel filter is also on the chip. the self-polling logic can be used to let the device operate autonomously as a master for a decoding microcontroller. 1.2 features low supply current (i s = 9 ma typ. receive, i s = 12ma typ. transmit mode, both at 3 v supply voltage, 25c) supply voltage range 2.1 v to 5.5 v operating temperature range -40c to +85c power down mode with very low supply current consumption fsk and ask modulation and demodulation capability without external circuitry changes, fm demodulation capability fully integrated vco and pll synthesizer and loop filter on-chip with on-chip crystal oscillator tuning, therefore no additional external components necessary differential receive signal path completely on-chip, therefore no external filters are necessary on-chip low pass channel select and data filter with tuneable bandwith data slicer with self-adjusting threshold and 2 peak detectors self-polling logic with adjustable duty cycle and ultrafast data rate detection and timer mode providing periodical interrupt fsk and ask sensitivity < -109 dbm adjustable lna gain digital rssi and battery voltage readout provides clock out pin for external microcontroller transmit power up to +13 dbm in 50 ? load at 5v supply voltage maximum datarate up to 64 kbaud manchester encoded i 2 c/3-wire microcontroller interface, working at max. 400kbit/s meets the etsi en300 220 regulation and cept erc 7003 recommendation tda5250 d2 version 1.7 product description data sheet 10 2007-02-26 1.3 application low bitrate communication systems keyless entry systems remote control systems alarm systems telemetry systems electronic metering home automation systems 1.4 package outlines pg-tssop-38.eps figure 1-1 pg-tssop-38 package outlines tda5250 d2 version 1.7 functional description data sheet 11 2007-02-26 2 functional description 2.1 pin configuration 5250d1_pin_conf.wmf figure 2-1 pin configuration vcc busmode lf ____ askfsk __ rxtx lni lnix gnd1 gndpa pa vcc1 pdn pdp slc vdd busdata busclk vss xout ci1 ci1x cq1 cq1x ci2 ci2x cq2 cq2x gnd rssi data ___ pwddd clkdiv ______ reset ___ en xgnd xswa xin xswf tda5250 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 tda5250 d2 version 1.7 functional description data sheet 12 2007-02-26 2.2 pin definitions and functions table 2-1 pin definition and function pin no. symbol equivalent i/o-schematic function 1 vcc analog supply (antiparallel diodes between vcc, vcc1, vdd) 2 busmode bus mode selection (i2c/3 wire bus mode selection) 3 lf loop filter and vco control voltage 4 askfsk ask/fsk- mode switch input 1 11 15 2 350 3 200 4 350 tda5250 d2 version 1.7 functional description data sheet 13 2007-02-26 5 rxtx rx/tx-mode switch input/output 6 lni rf input to differential low noise amplifier (lna)) 7 vcc see pin 6 analog supply (antiparallel diodes between vcc, vcc1, vdd 8 busmode bus mode selection (i2c/3 wire bus mode selection) 9 gndpa see pin 8 ground return for pa output stage 10 pa pa output stage 11 vcc1 see pin 1 supply for lna and pa 5 350 tx 6 5k 5k 7 pwdn 180 180 pwdn 1.1v 8 30 18 9 10 9 gndpa 10 ? tda5250 d2 version 1.7 functional description data sheet 14 2007-02-26 12 pdn output of the negative peak detector 13 pdp output of the positive peakdetector 14 slc slicer level for the data slicer 15 vdd see pin 1 digital supply 16 busdata bus data in/output 17 busclk bus clock input 18 vss see pin 8 ground for digital section 12 3k 50k 350 50k pwdn 13 3k 50k 350 50k pwdn 14 50k 350 50k 50k 50k 50k 50k 1.2ua 1.2ua 16 350 15k 17 350 tda5250 d2 version 1.7 functional description data sheet 15 2007-02-26 19 xout crystal oscillator output, can also be used as external reference frequency input. 20 xswf fsk modulation switch 21 xin see pin 20 22 xswa ask modulation/fsk center frequency switch 23 xgnd see pin 22 crystal oscillator ground return 24 en 3-wire bus enable input 19 4k 150 a vcc vcc-860mv 20 21 23 125ff ..... 4pf 250ff ..... 8pf 20 22 23 24 350 tda5250 d2 version 1.7 functional description data sheet 16 2007-02-26 25 reset reset of the entire system (to default values), active low 26 clkdiv clock output 27 pwddd power down input (active high), data detect output (active low) 28 data tx data input, rx data output (rx powerdown: pin 28 @ gnd) 29 rssi rssi output 25 350 110k 10p 26 350 27 350 30k 28 350 29 350 37k 16p s&h tda5250 d2 version 1.7 functional description data sheet 17 2007-02-26 30 gnd see pin 8 analog ground 31 cq2x pin for external capacitor q-channel, stage 2 32 cq2 ii q-channel, stage 2 33 ci2x ii i-channel, stage 2 34 ci2 ii i-channel, stage 2 35 cq1x ii q-channel, stage 1 36 cq1 ii q-channel, stage 1 37 ci1x ii i-channel, stage 1 38 ci1 ii i-channel, stage 1 31 stage1:vcc-630mv stage2: vcc-560mv tda5250 d2 version 1.7 functional description data sheet 18 2007-02-26 2.3 functional block diagram tda5250d1_blockdiagram_aktuell.wmf figure 2-2 main block diagram f if = 289.433mhz lna mixer lp filter quadri correlator vco tx/rx :12/16 phase det. charge p. loop filter ant f tx = 868.3mhz f rx = 1157.73mhz f rf = 868.3mhz data (rx/tx) clkdiv f = 289.433mhz f q = 18.0896mhz rssi single ended to differential conv. ant pwddd fsk data ask data gnd ask/fsk pa bandgap reference -peak det busdata busclk +peak det pdn pdp busmode + slicer - __ en vss gnd1 vdd lf tx/rx rxtx 6-bit sar-adc askfsk reset fsk ask 100k 100k lni lnix pa xout gndpa 14 16 17 24 2 28 26 27 5 4 13 12 25 29 18 30 8 21 19 3 9 10 6 7 i q vcc1 (lna/pa) vcc clk controller interface wakeup logic vcc 20 crystal osc, fskmod, finetuning xswf xswa xgnd xin 22 23 11 (lna/pa) 1 (analog) 15 (digital) data filter 100k slc 31 38 37 34 32 ci1 ci1x 33 ci2 ci2x 36 35 cq1 cq1x cq2 cq2x high/low gain rssi :4 0 90 (analog) (digital) mixer mixer channel filter channel filter limiter limiter ask/fsk tda5250 d2 version 1.7 functional description data sheet 19 2007-02-26 2.4 functional block description 2.4.1 power amplifier (pa) the power amplifier is operating in c-mode. it can be used in either high or low power mode. in high-power mode the transmit power is approximately +13dbm into 50 ohm at 5v and +4dbm at 2.1v supply voltage. in low power mode the transmit power is approximately -7dbm at 5v and - 32dbm at 2.1v supply voltage using the same matching network. the transmit power is controlled by the d0 -bit of the config register (subaddress 00h) as shown in the following table 2-2 . the default output power mode is high power mode. in case of ask modulation the power amplifier is turned fully on and off by the transmit baseband data, i.e. 100% on-off-keying. 2.4.2 low noise amplifier (lna) the lna is an on-chip cascode amplifier with a voltage gain of 15 to 20db and symmetrical inputs. it is possible to reduce the gain to 0 db via logic. 2.4.3 downconverter 1 st mixer the double balanced 1 st mixer converts the input frequency (rf) in the range of 868-870 mhz down to the intermediate frequency (if) at approximately 290mhz. the local oscillator frequency is generated by the pll synthesizer that is fully implemented on-chip as described in section 2.4.5 . this local oscillator operates at approximately 1157mhz in receive mode providing the above mentioned if frequency of 290mhz. the mixer is followed by a low pass filter with a corner frequency of approximately 350mhz in order to prevent rf and lo signals from appearing in the 290mhz if signal. 2.4.4 downconverter 2 nd i/q mixers the low pass filter is followed by 2 mixers (inphase i and quadrature q) that convert the 289mhz if signal down to zero-if. these two mixers are driven by a signal that is generated by dividing the local oscillator signal by 4, thus equalling the if frequency. table 2-2 sub address 00h: config bit function description default d0 pa_pwr 0= low tx power, 1= high tx power 1 table 2-3 sub address 00h: config bit function description default d4 lna_gain 0= low gain, 1= high gain 1 tda5250 d2 version 1.7 functional description data sheet 20 2007-02-26 2.4.5 pll synthesizer the phase locked loop synthesizer consists of two vcos (i.e. transmit and receive vco), a divider by 4, an asynchronous divider chain with selectable overall division ratio, a phase detector with charge pump and a loop filter and is fully implemented on-chip. the vcos are including spiral inductors and varactor diodes. the center frequency of the transmit vco is 868mhz, the center frequency of the receive vco is 1156mhz. generally in receive mode the relationship between local oscillator frequency f osc , the receive rf frequency f rf and the if frequency f if and thus the frequency that is applied to the i/q mixers is given in the following formula: f osc = 4/3 f rf = 4 f if the vco signal is applied to a divider by 4 whic h is producing approximately 289mhz signals in quadrature. the overall division ratio of the divider chain following the divider by 4 is 12 in transmit mode and 16 in receive mode as the nominal crystal oscillator frequency is 18.083mhz. the division ratio is controlled by the rxtx pin (pin 5) and the d10 bit in the config register. 2.4.6 i/q filters the i/q if to zero-if mixers are followed by baseband 6 th order low pass filters that are used for rf-channel filtering. iq_filter.wmf figure 2-3 one i/q filter stage the bandwidth of the filters is controlled by the values set in the filter-register. it can be adjusted between 50 and 350khz in 50khz steps via the bits d1 to d3 of the lpf register (subaddress 03h). 2.4.7 i/q limiters the i/q limiters are dc coupled multistage amplifiers with offset-compensating feedback circuit and an overall gain of approximately 80db each in the frequency range of 100hz up to 350khz. receive signal strength indicator (rssi) generators are included in both limiters which produce dc voltages that are directly proportional to the input signal level in the respective channels. the resulting i- and q-channel rssi-signals are summed to the nominal rssi signal. [2 ? 1] internal bus op tda5250 d2 version 1.7 functional description data sheet 21 2007-02-26 2.4.8 fsk demodulator the output differential signals of the i/q limiters are fed to a quadrature correlator circuit that is used to demodulate frequency shift keyed (fsk) signals. the demodulator gain is 2.4mv/khz, the maximum frequency deviation is 300khz as shown in figure 2-4 below. the demodulated signal is applied to the ask/fsk mode switch which is connected to the input of the data filter. the switch can be controlled by the askfsk pin (pin 4) and via the d11 bit in the config register. the modulation index m must be significantly larger than 2 and the deviation at least larger than 25khz for correct demodulation of the signal. qaudricorrelator.wmf figure 2-4 quadricorrelator demodulation characteristic 2.4.9 data filter the 2-pole data filter has a sallen-key architecture and is implemented fully on-chip. the bandwidth can be adjusted between approximately 5khz and 102khz via the bits d4 to d7 of the lpf register as shown in table 3-10 . 0,5 0,6 0,7 0,8 0,9 1 1,1 1,2 1,3 1,4 1,5 1,6 -350 -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 350 f /khz u /v tda5250 d2 version 1.7 functional description data sheet 22 2007-02-26 data_filter.wmf figure 2-5 data filter architecture 2.4.10 data slicer the data slicer is a fast comparator with a bandwidth of 100khz. the self-adjusting threshold is generated by a rc-network (lpf) or by use of one or both peak detectors depending on the baseband coding scheme as described in section 3.6 . this can be controlled by the d15 bit of the config register as shown in the following table. 2.4.11 peak detectors two separate peak detectors are available. they are generating dc voltages in a fast-attack and slow-release manner that are proportional to the positive and negative peak voltages appearing in the data signal. these voltages may be used to generate a threshold voltage for non-manchester encoded signals, for example. the time-constant of the fast-attack/slow-release action is determined by the rc network with external capacitor. 2.4.12 crystal oscillator the reference oscillator is an nic oscillator type (negative impedance converter) with a crystal operating in serial resonance. the nominal operating frequency of 18.083mhz and the frequencies for fsk modulation can be adjusted via 3 external capacitors. via microcontroller and bus interface the chip-internal capacitors can be used for finetuning of the nominal and the fsk modulation frequencies. this finetuning of the crystal oscillator allows to eliminate frequency errors due to crystal or component tolerances. 2.4.13 bandgap reference circuitry & powerdown a bandgap reference circuit provides a temperature stable 1.2v reference voltage for the device. a power down mode is available to switch off all subcircuits that are controlled by the bidirectional powerdown&datadetect pwddd pin (pin 27) as shown in the following table. powerdown mode can either be activated by pin 27 or bit d14 in register 00h. in powerdown mode also pin 28 (data) is affected (see section 2.4.17 ). table 2-4 sub address 00h: config bit function description default d15 slicer 0= lowpass filter, 1= peak detector 0 internal bus ask / fsk ota tda5250 d2 version 1.7 functional description data sheet 23 2007-02-26 2.4.14 timing and data control unit the timing and data control unit contains a wake-up logic unit, an i 2 c/3-wire microcontroller interface, a ?data valid? detection unit and a set of configuration registers as shown in the subsequent figure. logic.wmf figure 2-6 timing and data control unit the i 2 c / 3-wire bus interface gives an external microcontroller full control over important system parameters at any time. it is possible to set the device in three different modes: slave mode, self polling mode and timer mode. this is done by a state machine which is implemented in the wakeup logic unit. a detailed description is given in section 2.4.16 . table 2-5 pwddd pin operating states pwddd operating state vdd powerdown mode ground/vss device on i 2 c / 3wire interface 6 bit adc frequency window th1 tda5250 d2 version 1.7 functional description data sheet 25 2007-02-26 data transition: data transition on the pin busdata can only occur when busclk is low. busdata transitions while busclk is high will be interpreted as start or stop condition. start condition (sta): a start condition is defined by a high to low transition of the busdata line while busclk is high. this start condition must precede any command and initiate a data transfer onto the bus. stop condition (sto): a stop condition is defined by a low to high transition of the busdata line while busclk is high. this condition terminates the communication between the devices and forces the bus interface into the initial state. acknowledge (ack): indicates a successful data transfer. the transmitter will release the bus after sending 8 bit of data. during the 9th clock cycle the receiver will set the sda line to low level to indicate it has received the 8 bits of data correctly. data transfer write mode: to start the communication, the bus master must initiate a start condition (sta), followed by the 8bit chip address. the chip address for the tda5250 is fixed as ?1110000? (msb at first). the last bit (lsb=a0) of the chip address byte defines the type of operation to be performed: a0=0, a write operation is selected and a0=1 a read operation is selected. after this comparison the tda5250 will generate an ack and awaits the desired sub address byte (00h...0fh) and data bytes. at the end of the data transition the master has to generate the stop condition (sto). data transfer read mode: to start the communication in the read mode, the bus master must initiate a start condition (sta), followed by the 8 bit chip address (write: a0=0), followed by the sub address to read (80h, 81h), followed by the chip address (read: a0=1). after that procedure the data of the selected register (80h, 81h) is read out. during this time the data line has to be kept in high state and the chip sends out the data. at the end of data transition the master has to generate the stop condition (sto). bus data format in i 2 c mode table 2-7 chip address organization msb lsb function 1 1 1 0 0 0 0 0 chip address write 1 1 1 0 0 0 0 1 chip address read tda5250 d2 version 1.7 functional description data sheet 26 2007-02-26 * mandatory high 3-wire bus mode in this mode pin 2 (busmode)= high and pin 16 (busdata) is in the data input/output pin. pin 24 (en ) is used to activate the bus interface to allow the transfer of data to / from the device. when pin 24 (en ) is inactive (high), data transfer is inhibited. data transition: data transition on pin 16 (busdata) can only occur if the clock busclk is low. to perform a data transfer the interface has to be enabled. this is done by setting the en line to low. a serial transfer is done via busdata, busclk and en . the bit stream needs no chip address. data transfer write mode: to start the communication the en line has to be set to low. the desired sub address byte and data bytes have to follow. the subaddress (00h...0fh) determines which of the data bytes are transmitted. at the end of data transition the en must be high. data transfer read mode: to start the communication in the read mode, the en line has to be set to low followed by the sub address to read (80h, 81h). afterwards the device is ready to read out data. at the end of data transition en must be high. table 2-8 i 2 c bus write mode 8 bit msb chip address (write) lsb msb sub address (write) 00h...08h, 0dh, 0eh, 0fh lsb msb data in lsb sta 1 1 1 0 0 0 0 0 ack s7 s6 s5 s4 s3 s2 s1 s0 ack d7 d6 d5 d4 d3 d2 d1 d0 ack sto table 2-9 i 2 c bus write mode 16 bit msb chip address (write) lsb msb sub address (write) 00h...08h, 0dh, 0eh, 0fh lsb msb data in lsb sta 1 1 1 0 0 0 0 0 ack s7 s6 s5 s4 s3 s2 s1 s0 ack d15 ... d8 ack d7 d6 ... d0 ack sto table 2-10 i 2 c bus read mode msb chip address (write) lsb msb sub address (read) 80h, 81h lsb msb chip address (read) lsb sta 1 1 1 0 0 0 0 0 ack s7 s6 s5 s4 s3 s2 s1 s0 ack sta 1 1 1 0 0 0 0 1 ack table 2-10 i 2 c bus read mode (continued) msb data out from sub address lsb r7 r6 r5 r4 r3 r2 r1 r0 ack* sto tda5250 d2 version 1.7 functional description data sheet 27 2007-02-26 bus data format 3-wire bus mode register definition sub addresses overview register_overview.wmf figure 2-8 sub addresses overview table 2-11 3-wire bus write mode msb sub address (write) 00h...08h, 0dh, 0eh,0fh lsb msb data in x...0 (x=7 or 15) lsb s7 s6 s5 s4 s3 s2 s1 s0 dx ... d5 d4 d3 d2 d1 d0 table 2-12 3-wire bus read mode msb sub address (read) 80h, 81h lsb msb data out from sub address lsb s7 s6 s5 s4 s3 s2 s1 s0 r7 r6 r5 r4 r3 r2 r1 r0 wakeup adc rssi [8 bit] i 2 c - spi interface on_time [16 bit] off_time [16 bit] count_th1 [16bit] count_th2 [16bit] rssi_th3 [8 bit] control config [16 bit] status [8 bit] clk_div [8 bit] block_pd [16bit] xtal xtal_tune [16bit] fsk [16bit] xtal_config [8 bit] filter lpf [8 bit] tda5250 d2 version 1.7 functional description data sheet 28 2007-02-26 subaddress organization data byte specification note d3: function is only active in selfpolling and timer mode. when d3 is set to low the rx path is not enabled if pwddd pin is set to low. a delayed setting of d3 results in a delayed power on of the rx building blocks. table 2-13 sub addresses of data registers write msb lsb hex function description bit length 0 0 0 00 0 0 000h config general definition of status bits 16 0 0 0 00 0 0 101h fsk values for fsk-shift 16 0 0 0 00 0 1 002h xtal_tuning nominal frequency 16 0 0 0 00 0 1 103h lpf i/q and data filter cutoff frequencies 8 0 0 0 00 1 0 004h on_time on time of wakeup counter 16 0 0 0 00 1 0 105h off_time off time of wakeup counter 16 0 0 0 00 1 1 006h count_th1 lower threshold of window counter 16 0 0 0 00 1 1 107h count_th2 higher threshold of window counter 16 0 0 0 01 0 0 008h rssi_th3 threshold for rssi signal 8 0 0 0 01 1 0 10dh clk_div configuration and ratio of clock divider 8 0 0 0 01 1 1 00eh xtal_config xtal configuration 8 0 0 0 01 1 1 10fh block_pd building blocks power down 16 table 2-14 sub addresses of data registers read msb lsb hex function description bit length 1 0 0 00 0 0 080h status results of comparison: adc & window 8 1 0 0 00 0 0 181h adc adc data out 8 table 2-15 sub address 00h: config bit function description default d15 slicer 0= lowpass, 1= peak detector 0 d14 all_pd 0= normal operation, 1= all power down 0 d13 testmode 0= normal operation, 1=testmode 0 d12 control 0= rx/tx and ask/fsk external controlled, 1= register controlled 0 d11 ask_nfsk 0= fsk, 1=ask 0 d10 rx_ntx 0= tx, 1=rx 1 d9 clk_en 0= clk off during power down, 1= always clk on, ever in pd 0 d8 rx_data_inv 0= no data inversion, 1= data inversion 0 d7 d_out 0= data out if valid, 1= always data out 1 d6 adc_mode 0= one shot, 1= continuous 1 d5 f_count_mode 0= one shot, 1= continuous 1 d4 lna_gain 0= low gain, 1= high gain 1 d3 en_rx 0= disable receiver, 1= enable receiver (in self polling and timer mode) * 1 d2 mode_2 0= slave mode, 1= timer mode 0 d1 mode_1 0= slave or timer mode, 1= self polling mode 0 d0 pa_pwr 0= low tx power, 1= high tx power 1 tda5250 d2 version 1.7 functional description data sheet 29 2007-02-26 subaddress organization data byte specification note d3: function is only active in selfpolling and timer mode. when d3 is set to low the rx path is not enabled if pwddd pin is set to low. a delayed setting of d3 results in a delayed power on of the rx building blocks. table 2-16 sub addresses of data registers write msb lsb hex function description bit length 0 0 0 00 0 0 000h config general definition of status bits 16 0 0 0 00 0 0 101h fsk values for fsk-shift 16 0 0 0 00 0 1 002h xtal_tuning nominal frequency 16 0 0 0 00 0 1 103h lpf i/q and data filter cutoff frequencies 8 0 0 0 00 1 0 004h on_time on time of wakeup counter 16 0 0 0 00 1 0 105h off_time off time of wakeup counter 16 0 0 0 00 1 1 006h count_th1 lower threshold of window counter 16 0 0 0 00 1 1 107h count_th2 higher threshold of window counter 16 0 0 0 01 0 0 008h rssi_th3 threshold for rssi signal 8 0 0 0 01 1 0 10dh clk_div configuration and ratio of clock divider 8 0 0 0 01 1 1 00eh xtal_config xtal configuration 8 0 0 0 01 1 1 10fh block_pd building blocks power down 16 table 2-17 sub addresses of data registers read msb lsb hex function description bit length 1 0 0 00 0 0 0 80h status results of comparison: adc & window 8 1 0 0 00 0 0 1 81h adc adc data out 8 table 2-18 sub address 00h: config bit function description default d15 slicer 0= lowpass, 1= peak detector 0 d14 all_pd 0= normal operation, 1= all power down 0 d13 testmode 0= normal operation, 1=testmode 0 d12 control 0= rx/tx and ask/fsk external controlled, 1= register controlled 0 d11 ask_nfsk 0= fsk, 1=ask 0 d10 rx_ntx 0= tx, 1=rx 1 d9 clk_en 0= clk off during power down, 1= always clk on, ever in pd 0 d8 rx_data_inv 0= no data inversion, 1= data inversion 0 d7 d_out 0= data out if valid, 1= always data out 1 d6 adc_mode 0= one shot, 1= continuous 1 d5 f_count_mode 0= one shot, 1= continuous 1 d4 lna_gain 0= low gain, 1= high gain 1 d3 en_rx 0= disable receiver, 1= enable receiver (in self polling and timer mode) * 1 d2 mode_2 0= slave mode, 1= timer mode 0 d1 mode_1 0= slave or timer mode, 1= self polling mode 0 d0 pa_pwr 0= low tx power, 1= high tx power 1 tda5250 d2 version 1.7 functional description data sheet 30 2007-02-26 table 2-20 sub address 02h: xtal_tuning bit function value description default d15 not used 0 d14 not used 0 d13 not used 0 d12 not used 0 d11 not used 0 d10 not used 0 d9 not used 0 d8 not used 0 d7 not used 0 d6 not used 0 d5 nominal_frequ_5 8pf setting for nominal frequency ask-tx fsk-rx 0 d4 nominal_frequ_4 4pf 1 d3 nominal_frequ_3 2pf 0 d2 nominal_frequ_2 1pf 0 d1 nominal_frequ_1 500ff 1 d0 nominal_frequ_0 250ff 0 table 2-19 sub address 01h: fsk bit function value description default d15 not used 0 d14 not used 0 d13 fsk+5 8pf setting for positive frequency shift: +fsk or ask-rx 0 d12 fsk+4 4pf 0 d11 fsk+3 2pf 1 d10 fsk+2 1pf 0 d9 fsk+1 500ff 1 d8 fsk+0 250ff 0 d7 not used 0 d6 not used 0 d5 fsk-5 4pf setting for negative frequency shift: -fsk 0 d4 fsk-4 2pf 0 d3 fsk-3 1pf 1 d2 fsk-2 500ff 1 d1 fsk-1 250ff 0 d0 fsk-0 125ff 0 table 2-21 sub address 03h: lpf bit function description default d7 datafilter_3 3db cutoff frequency of data filter 0 d6 datafilter_2 0 d5 datafilter_1 0 d4 datafilter_0 1 d3 iq_filter_2 3db cutoff frequency of iq-filter 1 d2 iq_filter_1 0 d1 iq_filter_0 0 d0 not used 0 table 2-22 sub addresses 04h / 05h: on/off_time bit function default on_time default off_time d15 on_15 / off_15 1 1 d14 on_14 / off_14 1 1 d13 on_13 / off_13 1 1 d12 on_12 / off_12 1 1 d11 on_11 / off_11 1 0 d10 on_10 / off_10 1 0 d9 on_9 / off_9 1 1 d8 on_8 / off_8 0 1 d7 on_7 / off_7 1 1 d6 on_6 / off_6 1 0 d5 on_5 / off_5 0 0 d4 on_4 / off_4 0 0 d3 on_3 / off_3 0 0 d2 on_2 / off_2 0 0 d1 on_1 / off_1 0 0 d0 on_0 / off_0 0 0 table 2-23 sub address 06h: count_th1 bit function default d15 not used 0 d14 not used 0 d13 not used 0 d12 not used 0 d11 th1_11 0 d10 th1_10 0 d9 th1_9 0 d8 th1_8 0 d7 th1_7 0 d6 th1_6 0 d5 th1_5 0 d4 th1_4 0 d3 th1_3 0 d2 th1_2 0 d1 th1_1 0 d0 th1_0 0 table 2-24 sub address 07h: count_th2 bit function default d15 not used 0 d14 not used 0 d13 not used 0 d12 not used 0 d11 th2_11 0 d10 th2_10 0 d9 th2_9 0 d8 th2_8 0 d7 th2_7 0 d6 th2_6 0 d5 th2_5 0 d4 th2_4 0 d3 th2_3 0 d2 th2_2 0 d1 th2_1 0 tda5250 d2 version 1.7 functional description data sheet 31 2007-02-26 table 2-27 sub address 0eh: xtal_config bit function description default d7 not used 0 d6 not used 0 d5 not used 0 d4 not used 0 d3 not used 0 d2 fsk-ramp 0 only in bipolar mode 0 d1 fsk-ramp 1 0 d0 bipolar_fet 0= fet, 1=bipolar 1 table 2-28 sub address 0fh: block_pd bit function description default d15 ref_pd 1= power down band gap reference 1 d14 rc_pd 1= power down rc oscillator 1 d13 window_pd 1= power down window counter 1 d12 adc_pd 1= power down adc 1 d11 peak_det_pd 1= power down peak detectors 1 d10 data_slic_pd 1= power down data slicer 1 d9 data_fil_pd 1= power down data filter 1 d8 quad_pd 1= power down quadri correlator 1 d7 lim_pd 1= power down limiter 1 d6 i/q_fil_pd 1= power down i/q filters 1 d5 mix2_pd 1= power down i/q mixer 1 d4 mix1_pd 1= power down 1st mixer 1 d3 lna_pd 1= power down lna 1 d2 pa_pd 1= power down power amplifier 1 d1 pll_pd 1= power down pll 1 d0 xtal_pd 1= power down xtal oscillator 1 table 2-25 sub address 08h: rssi_th3 bit function description default d7 not used 1 d6 select 0= vcc, 1= rssi 1 d5 th3_5 1 d4 th3_4 1 d3 th3_3 1 d2 th3_2 1 d1 th3_1 1 d0 th3_0 1 table 2-26 sub address 0dh: clk_div bit function default d7 not used 0 d6 not used 0 d5 divmode_1 0 d4 divmode_0 0 d3 clkdiv_3 1 d2 clkdiv_2 0 d1 clkdiv_1 0 d0 clkdiv_0 0 table 2-29 sub address 80h: status bit function description d7 comp_low 1 if data rate < th1 d6 comp_in 1 if th1 < data rate < th2 d5 comp_high 1 if th2 < data rate d4 comp_0,5*low 1 if data rate < 0,5*th1 d3 comp_0,5*in 1 if 0,5*th1 < data rate < 0,5*th2 d2 comp_0,5*high 1 if 0,5*th2 < data rate d1 rssi=th3 1 if rssi value is equal th3 d0 rssi>th3 1 if rssi value is greater than th3 table 2-30 sub address 81h: adc bit function description d7 pd_adc adc power down feedback bit d6 select select feedback bit d5 rssi_5 rssi value bit5 d4 rssi_4 rssi value bit4 d3 rssi_3 rssi value bit3 d2 rssi_2 rssi value bit2 d1 rssi_1 rssi value bit1 d0 rssi_0 rssi value bit0 tda5250 d2 version 1.7 functional description data sheet 32 2007-02-26 2.4.16 wakeup logic 3_modes.wmf figure 2-9 wakeup logic states slave mode: the receive and transmit operation is fully controlled by an external control device via the respective rxtx , askfsk , pwddd , and data pins. the wakeup logic is inactive in this case. after reset or 1 st power-up the chip is in slave mode. by setting mode_1 and mode_2 in the config register the mode may be changed. self polling mode: the chip turns itself on periodically to receive using a built-in 32khz rc oscillator. the timing of this is determined by the on_time and off_time registers, the duty cycle can be set between 0 and 100% in 31.25s increments. the data detect logic is enabled and a 15s low impulse is provided at pwddd pin (pin 27), if the received data is valid. timing_selfpllmode.wmf figure 2-10 timing for self polling mode (adc & data detect in one shot mode) table 2-31 mode settings: config register mode_1 mode_2 mode 0 0 slave mode 0 1 timer mode 1 x self polling mode slave mode (default) mode_1 = 0 mode_2 = 0 self polling mode timer mode mode_1 = 1 mode_2 = x mode_1 = 0 mode_2 = 1 pwddd pin in self polling mode action rx on: valid data off_time t rx on: invalid data on_time on_time t min. 2.6ms 15s tda5250 d2 version 1.7 functional description data sheet 33 2007-02-26 note: the time delay between start of on time and the 15s low impulse is 2.6ms + 3 period of data rate. if adc & data detect logic are in continuous mode the 15s low impulse is applied at pwddd after each data valid decision. in self polling mode if d9=0 (register 00h) and when pwddd pin level is high the clk output is on during on time and off during off time. if d9=1, the clk output is always on. timer mode: only the internal timer (determined by the on_time and off_time registers) is active to support an external logic with periodical interrupts. after on_time + off_time a 15s low impulse is applied at the pwddd pin (pin 27). timing_timermode.wmf figure 2-11 timing for timer mode 2.4.17 data valid detection, data pin data signals generate a typical spectrum and this can be used to determine if valid data is on air. data_rate_detect.wmf figure 2-12 frequency and rssi window the ?data valid? criterion is generated from the result of rssi-th3 comparison and t gate between th1 and th2 result as shown below. in case of manchester coding the 0,5*th1 and 0,5*th2 gives improved performance. the use of permanent data valid recognition makes it absolutely necessary to set the rssi-adc and the window counter into continuous mode (register 00h, bit d5 = d6 = 1). action register 04h off_time t register 04h on_time on_time pwddd pin in timer mode t 15s 15s register 05h amplitude frequency rssi no data on air data on air frequency & rssi window f tda5250 d2 version 1.7 functional description data sheet 34 2007-02-26 data_valid.wmf figure 2-13 data valid circuit d_out and rx_data_inv from the config register determine the output of data at pin 28. rxtx int and tx_on are internally generated signals. in rx and power down mode data pin (pin 28) is tied to gnd. data_switch.wmf figure 2-14 data input/output circuit 2.4.18 sequence timer the sequence timer has to control all the enable signals of the analog components inside the chip. the time base is the 32 khz rc oscillator. after the first power on or reset a 1 mhz clock is available at the clock output pin. this clock output can be used by an external p to set the system into the desired state and outputs valid data after 500 s (see figure 2-15 and figure 2-16 , t clksu ) there are two possibilities to start the device after a reset or first power on: ? pwddd pin is low: normal operation timing is performed after t syssu (see figure 2-15 ). ? pwddd pin is high (device in power down mode): a clock is offered at the clock output pin until the device is activated (pwddd pin is pulled to low). after the first activation the time t syssu is required until normal operation timing is performed (see figure 2-16 ). this could be used to extend the clock generation without device programming or activation. note: it is required to activate the device for the duration of t syssu after first power on or a reset. only if this is done the normal operation timing is performed. 0,5*th1 t gate 0,5*th2 data valid th1 t gate th2 rssi th3 data data valid d_out rx data rx_data_inv tx data tx on rxtxint 28 tda5250 d2 version 1.7 functional description data sheet 35 2007-02-26 with default settings the clock generating units are disabled during pd, therefore no clock is available at the clock output pin. it is possible to offer a clock signal at the clock output pin every time (also during pd) if the clk_en bit in the config register is set to high. sequenzer_timing_pupstart.wmf figure 2-15 1 st start or reset in active mode note: the time values are typical values sequenzer_timing_pdstart.wmf figure 2-16 1st start or reset in pd mode * state is either ?i? or ?o? depending on time of setting into powerdown . note: the time values are typical values status xtal en dc offset compensation peak detector en reset or 1 st power on pwddd = low 8ms 2.2ms clock for external p 2.6ms datadetection en tx activ or rx activ rx activ tx activ rx activ power amp en 2.2ms 2.6ms 1.1ms 2.2ms 2.6ms pd if rx if rx if tx tx activ pd if rx t syssu t txsu t rxsu t ddsu t txsu 1.1ms t txsu 1.1ms t rxsu t rxsu t ddsu t ddsu 0.5ms t clksu t clksu 0.5ms t clksu 0.5ms ** status xtal en dc offset compensation peak detector en reset or 1 st power on pwddd = high clock for external p datadetection en pd pd tx activ rx activ power amp en if rx if rx if tx if rx tx activ or rx activ 8ms 1.1ms 2.2ms 2.6ms t syssu t txsu t rxsu t ddsu 2.2ms 2.6ms t txsu 1.1ms t rxsu t ddsu pwddd = low 0.5ms t clksu 0.5ms t clksu * tda5250 d2 version 1.7 functional description data sheet 36 2007-02-26 this means that the device needs t ddsu setup time to start the data detection after rx is activated. when activating tx it requires t txsu setup time to enable the power amplifier. for timing information refer to table 4.3 . for test purposes a testmode is provided by the sequencer as well. in this mode the block_pd register be set to various values. this will override the sequencer timing. depending on the settings in config register 00h the corresponding building blocks are enabled, as shown in the subsequent figure. sequencer_raw.wmf figure 2-17 sequencer?s capability 2.4.19 clock divider it supports an external logic with a programmable clock at pin 26 (clkdiv) . clk_div.wmf figure 2-18 clock divider the output selection and divider ratio can be set in the clk_div register. internal bus block_pd register ask/fsk tx on rx on switch 32 khz reset testmode all_pd 16 16 clk_en enable / disable building blocks rc- osc. 16 timing decode 2 xtal frequ. select 4 bit counter 18 mhz clkdiv internal bus divide by 2 switch 32 khz window count complete divmode_0 divmode_1 26 tda5250 d2 version 1.7 functional description data sheet 37 2007-02-26 note: data are valid 500 s after the crystal oscillator is enabled (see figure 2-15 and figure 2- 16 , t clksu ). note: as long as default settings are used, there is no clock available at the clock output during power down. it is possible to enable the clock during power down by setting clk_en (bit d9) in the config register (00h) to high. 2.4.20 rssi and supply voltage measurement the input of the 6bit-adc can be switched between two different sources: the rssi voltage (default setting) or a resistor network dividing the vcc voltage by 5. table 2-32 clk_div output selection d5 d4 output 0 0 output from divider (default) 0 1 18.089mhz 1 0 32khz 1 1 window count complete table 2-33 clk_div setting d3 d2 d1 d0 total divider ratio output frequency [mhz] 0 0 0 0 2 9,0 0 0 0 1 4 4,5 0 0 1 0 6 3,0 0 0 1 1 8 2,25 0 1 0 0 10 1,80 0 1 0 1 12 1,50 0 1 1 0 14 1,28 0 1 1 1 16 1,125 1 0 0 0 18 1,00 (default) 1 0 0 1 20 0,90 1 0 1 0 22 0,82 1 0 1 1 24 0,75 1 1 0 0 26 0,69 1 1 0 1 28 0,64 1 1 1 0 30 0,60 1 1 1 1 32 0,56 table 2-34 source for 6bit-adc selection (register 08h) select input for 6bit-adc 0 vcc / 5 1 rssi (default) tda5250 d2 version 1.7 functional description data sheet 38 2007-02-26 to prevent wrong interpretation of the adc information (read from register 81h: adc) you can use the adc- power down feedback bit (d7) and the select feedback bit (d6) which correspond to the actual measurement. note: as shown in section 2.4.18 there is a setup time of 2.6ms after rx activating. thus the measurement of rssi voltage does only make sense after this setup time. tda5250 d2 version 1.7 application data sheet 39 2007-02-26 3application 3.1 lna and pa matching 3.1.1 rx/tx switch rx/tx_switch.wmf figure 3-1 rx/tx switch the rx/tx-switch combines the pa-output and the lna-input into a single 50 ohm sma- connector. two pin-diodes are used as switching elements. if no current flows through a pin diode, it works as a high impedance for rf with very low capacitance. if the pin-diode is forward biased, it provides a low impedance path for rf. (some ? ) 3.1.2 switch in rx-mode the rx/tx-switch is set to the receive mode by either applying a high level or an open to the rx/ tx-jumper on the evalboard or by leaving it open. then both pin-diodes are not biased and therefore have a high impedance. l1 c4 c3 l2 c5 vcc tda5250 pa lni lnix rf i/o 50 ohm sma-connector rx/tx d1 d2 r1 c1 c2 c7 l3 c9 c10 rx/tx c6 tda5250 d2 version 1.7 application data sheet 40 2007-02-26 rx_mode.wmf figure 3-2 rx-mode the rf-signal is able to run from the rf-input-sma-connector to the lna-input-pin lni via c1, c2, c7, l3 and c9. r1 does not affect the matching circuit due to its high resistance. the other input of the differential lna lnix can always be ac-grounded using a large capacitor without any loss of performance. in this case the differential lna can be used as a single ended lna, which is easier to match. the s11 of the lna at pin lni on the evalboard is 0.945 / -47 (equals a resistor of 1.43kohm in parallel to a capacitor of 1.6pf) for both high and low-gain-mode of the lna. (pin lnix ac-grounded) this impedance has to be matched to 50 ohm with the parts c9, l3, c7 and c2. c1 is dc-decoupling-capacitor. on the evalboard the most important matching components are (shunt) l3 and (series) c2. the capacitors c7 and c9 are mainly dc-decoupling-capacitors and may be used for some fine tuning of the matching circuit. a good cae tool (featuring smith-chart) may be used for the calculation of the values of the components. however, the final values of the matching components always have to be found on the board because of the parasitics of the board, which highly influence the matching circuit at rf. l1 c4 c3 l2 c5 vcc tda5250 pa lni lnix rf i/o 50 ohm sma-connector rx/tx r1 c1 c2 c7 l3 c9 c10 rx/tx c6 open or vcc tda5250 d2 version 1.7 application data sheet 41 2007-02-26 measured magnitude of s11 of evalboard: s11_measured.pcx. figure 3-3 s11 measured above you can see the measured s11 of the evalboard. the ?3db-points are at 810mhz and 930mhz. so the 3db-bandwidth is: the loaded q of the resonant circuit is: the unloaded q of the resonant circuit is equal to the q of the inductor due to its losses. an approximation of the losses of the input matching network can be made with the formula: the noise figure of the lna-input-matching network is equal to its losses. the input matching network is always a compromise of sensitivity and selectivity. the loaded q should not get too high because of 2 reasons: more losses in the matching network and hence less sensitivity mhz mhz mhz f f b l u 120 810 930 = ? = ? = [3 ? 1] [3 ? 2] 2 . 7 120 3 , 868 = = = mhz mhz b f q center l mhz q q inductor u 868 @ 36 = [3 ? 3] [3 ? 4] db q q loss u l 2 36 2 . 7 1 log 20 1 log 20 = ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? = tda5250 d2 version 1.7 application data sheet 42 2007-02-26 tolerances of components affect matching too much. this will cause problems in a tuning-free mass production of the application. a good cae-tool will help to see the effects of component tolerances on the input matching more accurate by tweaking each value. a very high selectivity can be reached by using saw-filters at the expense of higher cost and lower sensitivity which will be reduced by the losses of the saw-filter of approx. 4db. image-suppression: due to the quite high 1 st -if of the frontend, the image frequency is quite far away. the image frequency of the receiver is at: the image suppression on the evalboard is about 16db. lo-leakage: the lo of the 1 st mixer is at: the lo-leakage of the evalboard on the rf-input is about ?98dbm. this is far below the etsi- radio-regulation-limit for lo-leakage. 3.1.3 switch in tx-mode the evalboard can be set into the tx-mode by grounding the rx/tx-jumper on the evalboard or programming the tda5250 to operate in the tx-mode. if the ic is programmed to operate in the tx-mode, the rx/tx-pin will act as an open drain output at a logical low. then a dc-current can flow from vcc to gnd via l1, l2, d1, r1 and d2. now both pin-diodes are biased with a current of approx. 0.3ma@3v and have a very low impedance for rf. mhz mhz f f f if signal image 2 . 1447 4 . 289 * 2 3 . 868 2 = + = ? + = [3 ? 5] [3 ? 6] [3 ? 7] mhz mhz f f receive lo 73 . 1157 3 4 3 . 868 3 4 * = ? = = 1 , 2 r v vcc i diode pin forward diode pin ? ? ? ? = tda5250 d2 version 1.7 application data sheet 43 2007-02-26 tx_mode.wmf figure 3-4 tx_mode r1 does not influence the matching because of its very high resistance. due to the large capacitance of c1, c6 and c5 the circuit can be further simplified for rf: tx_mode_simplified.wmf figure 3-5 tx_mode_simplified the lna-matching is rf-grounded now, so no power is lost in the lna-input. the pa-matching consists of c2, c3 l2, c4 and l1. when designing the matching of the pa, c2 must not be changed anymore because its value is already fixed by the lna-input-matching. l1 c4 c3 l2 c5 vcc tda5250 pa lni lnix rf i/o 50 ohm sma-connector rx/tx r1 c1 c2 c7 l3 c9 c10 rx/tx c6 grounded (with jumper or rx/tx-pin of ic) l1 c4 c3 l2 tda5250 pa lni lnix rf i/o 50 ohm sma-connector c2 c7 l3 c9 c10 tda5250 d2 version 1.7 application data sheet 44 2007-02-26 3.1.4 power-amplifier the power amplifier operates in a high efficient class c mode. this mode is characterized by a pulsed operation of the power amplifier transistor at a current flow angle of << . a frequency selective network at the amplifier output passes the fundamental frequency component of the pulse spectrum of the collector current to the load. the load and its resonance transformation to the collector of the power amplifier can be generalized by the equivalent circuit of figure 3-6 . the tank circuit l//c//rl in parallel to the output impedance of the transistor should be in resonance at the operating frequency of the transmitter. equivalent_power_wmf. figure 3-6 equivalent power amplifier tank circuit the optimum load at the collector of the power amplifier for ?critical? operation under idealized conditions at resonance is: a typical value of r lc for an rf output power of p o = 13mw is: critical? operation is characterized by the rf peak voltage swing at the collector of the pa transistor to just reach the supply voltage v s . the high efficiency under ?critical? operating conditions can be explained by the low power loss at the transistor. during the conducting phase of the transistor there is no or only a very small collector voltage present, thus minimizing the power loss of the transistor (i c *u ce ). this is particularly true for low current flow angles of << . in practice the rf-saturation voltage of the pa transistor and other parasitics will reduce the ?critical? r lc . the output power p o will be reduced when operating in an ?overcritical? mode at a r l > r lc . as shown in figure 3-7, however, power efficiency e (and bandwidth) will increase by some degree when operating at higher r l . the collector efficiency e is defined as v s r l c l o s lc p v r 2 2 = [3 ? 8] ? = ? = 350 013 . 0 2 3 2 lc r [3 ? 9] tda5250 d2 version 1.7 application data sheet 45 2007-02-26 the diagram of figure 3-7 has been measured directly at the pa-output at v s =3v. a power loss in the matching circuit of about 2db will decrease the output power. as shown in the diagram, 240 ohm is the optimum impedance for operation at 3v. for an approximation of r opt and p out at other supply voltages those 2 formulas can be used: and power_e_vs_rl.wmf figure 3-7 output power p o (mw) and collector efficiency e vs. load resistor r l . the dc collector current i c of the power amplifier and the rf output power p o vary with the load resistor r l . this is typical for overcritical operation of class c amplifiers. the collector current will show a characteristic dip at the resonance frequency for this type of ?overcritical? operation. the depth of this dip will increase with higher values of r l . as figure 3-8 shows, detuning beyond the bandwidth of the matching circuit results in a significant increase of collector current of the power amplifier and in some loss of output power. this diagram shows the data for the circuit of the test board at the frequency of 868 mhz. the effective load resistor of this circuit is r l = 240ohm, which is the optimum impedance for operation at 3v. this will lead to a dip of the collector current f approx. 20%. c s o i v p e = [3 ? 10] s opt v r ~ [3 ? 11] [3 ? 12] opt out r p ~ tda5250 d2 version 1.7 application data sheet 46 2007-02-26 pout_vs_frequ.wmf figure 3-8 power output and collector current vs. frequency c4, l2 and c3||c2 are the main matching components which are used to transform the 50 ohm load at the sma-rf-connector to a higher impedance at the pa-output (240ohm@3v). l1 can be used for finetuning of the resonance frequency but should not be too low in order to keep its loss low. the transformed impedance of 240ohm+j0 at the pa-output-pin can be verified with a network analyzer using this measurement procedure: 1. calibrate your network analyzer. 2. connect a short, low-loss 50 ohm cable to your network analyzer with an open end on one side. semirigid cable works best. 3. use the ?port extension? feature of your network analyzer to shift the reference plane of your network analyzer to the open end of the cable. 4. connect the center-conductor of the cable to the solder pad of the pin ?pa? of the ic. the shield has to be grounded. very short connections must be used. do not remove the ic or any part of the matching-components! 5. screw a 50ohm-dummy-load on the rf-i/o-sma-connector 6. the tda5250 has to be in ask-tx-mode, data-input=low. 7. be sure that your network analyzer is ac-coupled and turn on the power supply of the ic. 8. measure the s-parameter tda5250 d2 version 1.7 application data sheet 47 2007-02-26 sparam_measured_200m.pcx figure 3-9 sparam_measured_200m above you can see the measurement of the evalboard with a span of 200mhz. the evalboard has been optimized for 3v. the load is about 240+j0 at 868.3mhz. a tuning-free realization requires a careful design of the components within the matching network. a simple linear cae-tool will help to see the influence of tolerances of matching components. suppression of spurious harmonics may require some additional filtering within the antenna matching circuit. both can be seen in figure 3-10 and figure 3-11 the total spectrum of the evalboard can be summarized as: carrier fc +9dbm fc-18.1mhz -62dbm fc+18.1mhz -66dbm 2 nd harmonic -40dbm 3 rd harmonic -44dbm tda5250 d2 version 1.7 application data sheet 48 2007-02-26 oberwellentx.tif figure 3-10 transmit spectrum 13.2ghz spektrum_10r_3v.tif figure 3-11 transmit spectrum 300mhz regarding cept erc recommendation 70-03 and etsi regulation en 300220 both of the following figures show full compliance in case of ask and fsk modulation spectrum. data signal is a manchester encoded prbs9 (pseudo random binary sequence), rf output power is +9dbm at a supply voltage of 3v. with these settings ask allows a maximum data rate of 25kbaud, in fsk case 40kbaud are possible. see also section 4.1.4 tda5250 d2 version 1.7 application data sheet 49 2007-02-26 ask_25kbaud_manch_prbs9_10dbm_3v_spectrum_cept_erc7003.wmf figure 3-12 ask transmit spectrum 25kbaud, manch, prbs9, 9dbm, 3v fsk_40kbaud_manch_prbs9_10dbm_3v_spectrum_cept_erc7003.wmf figure 3-13 fsk transmit spectrum 40kbaud, manch, prbs9, 9dbm, 3v tda5250 d2 version 1.7 application data sheet 50 2007-02-26 3.2 crystal oscillator the equivalent schematic of the crystal with its parameters specified by the crystal manufacturer can be taken from the subsequent figure. here also the load capacitance of the crystal c l , which the crystal wants to see in order to oscillate at the desired frequency, can be seen. crystal.wmf figure 3-14 crystal l 1 : motional inductance of the crystal c 1 : motional capacitance of the crystal c 0 : shunt capacitance of the crystal therefore the resonant frequency f s of the crystal is defined as: the series load resonant frequency f s ? of the crystal is defined as: regarding figure 3-14 f s ? is the nominal frequency of the crystal with a specified load when tested by the crystal manufacturer. pulling sensitivity of the crystal is defined as the magnitude of the relative change in frequency relating to the variation of the load capacitor. l 1 c 1 r 1 c 0 c l -r [3 ? 14] 1 1 * 2 1 c l f s = l s c c c c l f + + = 0 1 1 1 1 * * 2 1 ` [3 ? 13] tda5250 d2 version 1.7 application data sheet 51 2007-02-26 choosing c l as large as possible results in a small pulling sensitivity. on the other hand a small c l keeps the influence of the serial inductance and the tolerances associated to it small (see formula [3-17] ). start-up time where: -r: is the negative impedance of the oscillator see figure 3-15 r ext : is the sum of all external resistances (e.g. r 1 or any other resistance that may be present in the circuit, see figure 3-14 the proportionality of l 1 and c 1 of the crystal is defined by formula [3-13] . for a crystal with a small c 1 the start -up time will also be slower. typically the lower the value of the crystal frequency, the lower the c 1 . a short conclusion regarding crystal and crystal oscillator dependencies is shown in the following table: the crystal oscillator in the tda5250 is a nic (negative impedance converter) oscillator type. the input impedance of this oscillator is a negative impedance in series to an inductance. therefore the load capacitance of the crystal c l (specified by the crystal supplier) is transformed to the capacitance c v as shown in formula [3-17]. table 3-1 crystal and crystal oscilator dependency result independent variable relative tolerance maximum deviation t start-up c 1 > >> >> < c 0 > << - frequency of quartz > >>> > << l osc > >> > - c l > >< - () 2 0 1 2 l l s s l c c c c f f c d + ? = = [3 ? 15] ext start r r l t ? ? 1 ~ [3 ? 16] tda5250 d2 version 1.7 application data sheet 52 2007-02-26 qosz_nic.wmf figure 3-15 crystal oscillator c l : crystal load capacitance for nominal frequency : angular frequency l osc : inductivity of the crystal oscillator - typ: 2.7 h with pad of board 2.45 h without pad with the aid of this formula it becomes obvious that the higher the serial capacitance c v is, the higher is the influence of l osc . the tolerance of the internal oscillator inductivity is much higher, so the inductivity is the dominating value for the tolerance. fsk modulation and tuning are achieved by a variation of c v . in case of small frequency deviations (up to +/- 1000 ppm), the desired load capacitances for fsk modulation are frequency depending and can be calculated with the formula below. c l : crystal load capacitance for nominal frequency c 0 : shunt capacitance of the crystal c 1 : motional capacitance of the crystal f: crystal oscillator frequency n: division ratio of the pll -r l osc f, c l c v tda 5250 osc l v osc v l l c c l c c 2 2 1 1 1 1 + = ? ? = [3 ? 17] c l c l c 0 ? f nf ? ---------- 1 2c 0 c l + () ? c 1 --------------------------------- + ?? ?? ?? ?? + ? 1 ? f nf ? ---------- 1 2c 0 c l + () ? c 1 --------------------------------- + ?? ?? ?? ? ------------------------------------------------------------------------------------------ = [3 ? 18] tda5250 d2 version 1.7 application data sheet 53 2007-02-26 ? f: peak frequency deviation with c l+ and c l- the necessary c v+ for fsk high and c v- for fsk low can be calculated. alternatively, an external ac coupled (10nf in series to 1k ? ) signal can be applied at pin 19 (xout) . the drive level should be approximately 100mvpp. 3.2.1 synthesizer frequency setting generating ask and fsk modulation 3 setable frequencies are necessary. 3.2.1.1 possible crystal oscillator frequencies the resulting possible crystal oscillator frequencies are shown in the following figure 3-16 free_reg.wmf figure 3-16 possible crystal oscillator frequencies in ask receive mode the crystal oscillator is set to frequency f 2 to realize the necessary frequency offset to receive the ask signal at f 0 *n (n: division ratio of the pll). to set the 3 different frequencies 3 different c v are necessary. via internal switches 3 external capacitors can be combined to generate the necessary c v in case of ask- or fsk-modulation. internal banks of switchable capacitors allow the finetuning of these frequencies. 3.2.2 transmit/receive ask/fsk frequency assignment depending on whether the device operates in transmit or receive mode or whether it operates in ask or fsk the following cases can be distinguished: 3.2.2.1 fsk-mode in transmit mode the two frequencies representing logical high and low data states have to be adjusted depending on the intended frequency deviation and separately according to the following formulas: nominal frequency deviation deviation rx: fsk ask tx: fsk- ask fsk+ f f f 0 1 2 tda5250 d2 version 1.7 application data sheet 54 2007-02-26 f cosc hi = (f rf + f dev ) / 48 f cosc low = (f rf - f dev ) / 48 e.g. f cosc hi = (868,3e6 + 50e3) / 48 = 18.08438mhz f cosc low = (868,3e6 - 50e3) / 48 = 18.08229mhz with a frequency deviation of 50khz. figure 3-17 shows the configuration of the switches and the capacitors to achieve the 2 desired frequencies. gray parts of the schematics indicate inactive parts. for fsk modulation the ask- switch is always open. for fsk low the fsk-switch is closed and c v2 and c tune2 are bypassed. the effective c v- is given by: for finetuning c tune1 can be varied over a range of 8 pf in steps of 125ff. the switches of this c- bank are controlled by the bits d0 to d5 in the fsk register (subaddress 01h, see table 3-6 ). for fsk high the fsk-switch is open. so the effective c v+ is given by: the c-bank c tune2 can be varied over a range of 16 pf in steps of 250ff for finetuning of the fsk high frequency. the switches of this c-bank are controlled by the bits d8 to d13 in the fsk register (subaddress 01h, see table 3-6 ). [3 ? 19] 1 1 tune v v c c c + = ? [3 ? 20] c v+ c v1 c tune1 + () c v2 c tune2 + () ? c v1 c tune1 +c v2 c tune2 + + -------------------------------------------------------------------------------------- - = [3 ? 21] fsk high xout 19 xin 21 xswf 20 xswa 22 xgnd 23 -r l ask- switch fsk- switch fsk low xout 19 xin 21 xswf 20 xswa 22 xgnd 23 -r l ask- switch fsk- switch c v1 c v2 c v3 f, c l c v1 c v2 c v3 f, c l c tune1 c tune2 c tune1 c tune2 tda5250 d2 version 1.7 application data sheet 55 2007-02-26 qosc_fsk.wmf figure 3-17 fsk modulation in receive mode the crystal oscillator frequency is set to yield a direct-to-zero conversion of the receive data. thus the frequency may be calculated as f cosc = f rf / 48, e.g. f cosc = 868,3e6 / 48 = 18.0833mhz which is identical to the ask transmit case. qosc_ask.wmf figure 3-18 fsk receive in this case the ask-switch is closed. the necessary c vm is given by: the c-bank c tune2 can be varied over a range of 16 pf in steps of 250ff for finetuning of the fsk receive frequency. in this case the switches of the c-bank are controlled by the bits d0 to d5 of the xtal_tuning register (subaddress 02h, see table 3-5 ). 3.2.2.2 ask-mode: in transmit mode the crystal oscillator frequency is the same as in the fsk receive case, see figure 3-18 . in receive mode a receive frequency offset is necessary as the limiters feedback is ac-coupled. this offset is achieved by setting the oscillator frequency to the fsk high transmit frequency, see figure 3-17 . [3 ? 22] xout 19 xin 21 xswf 20 xswa 22 xgnd 23 -r l ask- switch fsk- switch c v1 c v2 c v3 f, c l c tune1 c tune2 c vm c v1 c tune1 + () c v2 c + v3 c tune2 + () ? c v1 c tune1 +c v2 c + v3 c tune2 + + ------------------------------------------------------------------------------------------------------- - = [3 ? 23] tda5250 d2 version 1.7 application data sheet 56 2007-02-26 3.2.3 parasitics for the correct calculation of the external capacitors the parasitic capacitances of the pins and the switches (c 20 , c 21 , c 22 ) have to be taken into account. qosc_parasitics.wmf figure 3-19 parasitics of the switching network with the given parasitics the actual c v can be calculated: table 3-2 typical values of parasitic capacitances name value c 20 4,5 pf c 21 fsk-: 2,8 pf / fsk+&ask: 2.3pf c 22 1,3 pf xout 19 xin 21 xswf 20 xswa 22 xgnd 23 c v1 c v2 c v3 c tune1 c tune2 f, c l -r l c 21 c 22 c 20 c v- c v1 c tune1 c 21 ++ = c v+ c v1 c tune1 + () c v2 c 20 c + tune2 + () ? c v1 c tune1 +c v2 c 20 c + tune2 + + ------------------------------------------------------------------------------------------------------- c 21 + = c vm c v1 c tune1 + () c v2 c 20 c ++ v3 c 22 c + tune2 + () ? c v1 c tune1 +c v2 c 20 c ++ v3 c 22 c + tune2 + + ------------------------------------------------------------------------------------------------------------------------------- ---------- c 21 + = [3 ? 24] [3 ? 26] tda5250 d2 version 1.7 application data sheet 57 2007-02-26 note : please keep in mind also to include the pad parasitics of the circuit board. 3.2.4 calculation of the external capacitors 1. determination of necessary crystal frequency using formula [4-19]. e.g. f fsk- = f cosc low 2. determine corresponding c load applying formula [4-18] . e.g. c l fsk - = c l 3. necessary c v using formula [4-17] . e.g. 1. when the necessary c v for the 3 frequencies (c v- for fsk low, c v+ for fsk high and c vm for fsk-receive) are known the external capacitors and the internal tuning caps can be calculated using the following formulas: to compensate frequency errors due to crystal and component tolerance c v1 , c v2 and c v3 have to be varied. to enable this correction, half of the necessary capacitance variation has to be realized with the internal c-banks. if no finetuning is intended it is recommended to leave xin (pin 21) open. so the parasitic capacitance of pin 21 has no effect. note : please keep in mind also to include the pad parasitics of the circuit board. in the suitable range for the serial capacitor, either capacitors with a tolerance of 0.1pf or 1% are available. a spreadsheet, which can be used to predict the total frequency error by simply entering the crystal specification, may be obtained from infineon. 3.2.5 fsk-switch modes the fsk-switch can be used either in a bipolar or in a fet mode. the mode of this switch is controlled by bit d0 of the xtal_config register (subaddress 0eh). [3 ? 25] [3 ? 25] () osc fsk fsk l v l f c c * 2 1 1 2 , ? ? ? + = [3 ? 29] c v1 c tune1 +c v- c 21 ? = c v2 c tune2 + c v1 c tune1 + () c v+ c 21 ? () ? c v1 c tune1 + () c v+ c 21 ? () ? ---------------------------------------------------------------------- c 20 ? = c v3 c tune2 + c v1 c tune1 + () c vm c 21 ? () ? c v1 c tune1 + () c vm c 21 ? () ? ------------------------------------------------------------------------ -c 20 ?c v2 ?c 22 ? = -fsk: +fsk: fsk_rx: [3 ? 27] [3 ? 28] tda5250 d2 version 1.7 application data sheet 58 2007-02-26 in the bipolar mode the fsk-switch can be controlled by a ramp function. this ramp function is set by the bits d1 and d2 of the xtal_config register (subadress 0eh). with these modes of the fsk-switch the bandwidth of the fsk spectrum can be influenced. when working in the fet mode the power consumption can be reduced by about 200 a. the default mode is bipolar switch with no ramp function (d0 = 1, d1 = d2 = 0), which is suitable for all bitrates. 3.2.6 finetuning and fsk modulation relevant registers case fsk-rx or ask-tx (c tune2 ) : case fsk-tx or ask-rx (c tune1 and c tune2 ): table 3-3 sub address 0eh: xtal_config d0 d1 d2 switch mode ramp time max. bitrate 0 n.a. n.a. fet < 0.2 s > 32 kbit/s nrz 1 00 bipolar (default) < 0.2 s > 32 kbit/s nrz 1 10 bipolar 4 s 32 kbit/s nrz 1 01 bipolar 8 s 16 kbit/s nrz 1 11 bipolar 12 s 12 kbit/s nrz table 3-4 sub address 02h: xtal_tuning bit function value description default d5 nominal_frequ_5 8pf setting for nominal frequency 0 d4 nominal_frequ_4 4pf 1 d3 nominal_frequ_3 2pf 0 d2 nominal_frequ_2 1pf ask-tx fsk-rx 0 d1 nominal_frequ_1 500ff 1 d0 nominal_frequ_0 250ff (c tune2 ) 0 table 3-5 sub address 01h: fsk bit function value description default d13 fsk+5 8pf setting for positive frequency shift: +fsk or ask-rx 0 d12 fsk+4 4pf 0 d11 fsk+3 2pf 1 d10 fsk+2 1pf 0 d9 fsk+1 500ff 1 d8 fsk+0 250ff (c tune2 ) 0 tda5250 d2 version 1.7 application data sheet 59 2007-02-26 default values in case of using the evaluation board, the crystal with its typical parameters (fp=18.08958mhz, c 1 =8ff, c 0 =2,08pf, c l =12pf) and external capacitors with cv1=4.7pf, cv2=1.8pf, cv3=12pf each are used the following default states are set in the device . 3.2.7 chip and system tolerances quartz: fp=18.08958mhz; c1=8ff; c0=2,08pf; cl=12pf (typical values) cv1=4.7pf, cv2=1.8pf, cv3=12pf tolerance values in table 3-8 are valid, if pin 21 is not connected. establishing the connection to pin 21 the tolerances increase by +/- 20ppm (internal capacitors), if internal tuning is not used. d5 fsk-5 4pf setting for negative frequency shift: -fsk 0 d4 fsk-4 2pf 0 d3 fsk-3 1pf 1 d2 fsk-2 500ff 1 d1 fsk-1 250ff 0 d0 fsk-0 125ff (c tune1 ) 0 table 3-6 default oscillator settings operating state frequency ask-tx / fsk-rx 868.3 mhz +fsk-tx / ask-rx +50 khz -fsk-tx -50 khz table 3-7 internal tuning part frequency tolerance @ 868mhz rel. tolerance frequency set accuracy +/- 3khz +/- 3.5ppm temperature (-40...+85c) +/- 5khz +/- 6ppm supply voltage(2.1...5.5v) +/- 1.5khz +/- 1.5ppm total +/- 9.5khz +/- 11ppm table 3-8 default setup (without internal tuning & without pin21 usage) part frequency tolerance @ 868mhz rel. tolerance internal capacitors (+/- 10%) +/- 8khz +/- 9ppm inductivity of the crystal oscillator +/- 18khz +/- 21ppm temperature (-40...+85c) +/- 5khz +/- 6ppm supply voltage (2.1...5.5v) +/- 1khz +/- 1.5ppm total +/- 32khz +/- 37.5ppm tda5250 d2 version 1.7 application data sheet 60 2007-02-26 concerning the frequency tolerances of the whole system also crystal tolerances (tuning tolerances, temperature stability, tolerance of c l ) have to be considered. in addition to the chip tolerances also the crystal and external component tolerances have to be considered in the tuning and non-tuning case. in case of internal tuning: the crystal on the evaluation board has a temperature stability of +/- 20ppm (or +/- 17khz), which must be added to the total tolerances. in case of default setup (without internal tuning and without usage of pin 21) the temperature stability and tuning tolerance of the crystal as well as the tolerance of the external capacitors (+/- 0.1pf) have to be added. the crystal on the evaluation board has a temperature stability of +/- 20ppm (or +/- 17khz) and a tuning tolerance of +/- 10ppm (or +/- 8.5 khz).the external capacitors add a tolerance of +/- 4ppm (or +/- 3.5khz). the frequency stabilities of both the receiver and the transmitter and the modulation bandwidth set the limit for the bandwidth of the iq filter. to achieve a high receiver sensitivity and efficient suppression of adjacent interference signals, the narrowest possible iq bandwidth should be realized ( see section 3.3 ). 3.3 iq-filter the iq-filter should be set to values corresponding to the rf-bandwidth of the received rf signal via the d1 to d3 bits of the lpf register (subaddress 03h). table 3-9 3db cutoff frequencies i/q filter d3 d2 d1 nominal f -3db in khz (programmable) resulting effective channel bandwidth in khz 0 0 0 not used 0 0 1 350 700 0 1 0 250 500 0 1 1 200 400 1 0 0 150 (default) 300 1 0 1 100 200 1 1 0 50 100 1 1 1 not used tda5250 d2 version 1.7 application data sheet 61 2007-02-26 iq_filter_curve.wmf figure 3-20 i/q filter characteristics iq_char.wmf figure 3-21 iq filter and frequency characteristics of the receive system 3.4 data filter the data-filter should be set to values corresponding to the bandwidth of the transmitted data signal via the d4 to d7 bits of the lpf register (subaddress 03h). -80 -70 -60 -50 -40 -30 -20 -10 0 10 10 10 0 10 0 0 10 0 0 0 f [khz] 50 khz 10 0 k hz 15 0 k h z 200khz 250khz 350khz iq filter f 3db -f iq filter f 3db effective channel bandwidth f tda5250 d2 version 1.7 application data sheet 62 2007-02-26 3.5 limiter and rssi the i/q limiters are dc coupled multistage amplifiers with offset-compensating feedback circuit and an overall gain of approximately 80db each in the frequency range of 100hz up to 350khz. receive signal strength indicator (rssi) generators are included in both limiters which produce dc voltages that are directly proportional to the input signal level in the respective channels. the resulting i- and q-channel rssi-signals are summed to the nominal rssi signal. limiter input.wmf figure 3-22 limiter and pinning table 3-10 3db cutoff frequencies data filter d7 d6 d5 d4 nominal f -3db in khz 0 0 0 0 5 0 0 0 1 7 (default) 0 0 1 0 9 0 0 1 1 11 0 1 0 0 14 0 1 0 1 18 0 1 1 0 23 0 1 1 1 28 1 0 0 0 32 1 0 0 1 39 1 0 1 0 49 1 0 1 1 55 1 1 0 0 64 1 1 0 1 73 1 1 1 0 86 1 1 1 1 102 38 ci1 37 36 35 34 33 32 31 ci1x cq1 cq1x ci2 ci2x cq2 cq2x i- filter f g q- filter f g c c c c c c c c q limiter limiter i rssi 29 c rssi quadr. corr. quadr. corr. 37k tda5250 d2 version 1.7 application data sheet 63 2007-02-26 the dc offset compensation needs 2.2ms after power on or tx/rx switch. this time is hard wired and independent from external capacitors c c on pins 31 to 38. the maximum value for this capacitors is 47nf. rssi accuracy settling time = 2.2ms + 5*rc=2.2ms+5*37k*2.2nf=2.6ms r - internal resistor; c - external capacitor at pin 29 limiter_char.wmf figure 3-23 limiter frequency characteristics table 3-11 limiter bandwidth cc [nf] f3db lower limit [hz] f3db upper limit comment 220 100 iq filter setup time not guaranteed 100 220 - ll - setup time not guaranteed 47 470 - ll - eval board 22 1000 - ll - 10 2200 - ll - v [db] f 0 80 iq filter f 3db f 3db limiter lower limit f 3db tda5250 d2 version 1.7 application data sheet 64 2007-02-26 rssi.wmf figure 3-24 typ. rssi level (eval board) @3v 3.6 data slicer - slicing level the data slicer is an analog-to-digital converter. it is necessary to generate a threshold value for the negative comparator input (data slicer). the tda5250 offers an rc integrator and a peak detector which can be selected via logic. independent of the choice, the peak detector outputs are always active. 3.6.1 rc integrator necessary external component ( pin14 ): c slc this integrator generates the mean value of the data filter output. for a stable threshold value, the cut-off frequency has to be lower than the lowest signal frequency. the cutoff frequency results from the internal resistance r=100k ? and the external capacitor c slc on pin14 . cut-off frequency: component calculation: (rule of thumb) t l ? longest period of no signal change table 3-12 sub address 00h: config bit function description default set d15 slicer 0= lp, 1= peak detector 0 0 adc 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 rf /dbm rssi /mv high gain low gain {} signal slc off cut f min c k f < ? ? ? = ? 100 2 1 [3 ? 30] ? ? k t c l slc 100 3 [3 ? 31] tda5250 d2 version 1.7 application data sheet 65 2007-02-26 slc_rc.wmf figure 3-25 slicer level using rc integrator 3.6.2 peak detectors the tda5250 has two peak detectors built in, one for positive peaks in the data stream and the other for the negative ones. necessary external components: - pin12: c n - pin13: c p table 3-13 sub address 00h: config bit function description default set d15 slicer 0= lp, 1= peak detector 0 1 tda5250 d2 version 1.7 application data sheet 66 2007-02-26 slc_pkd.wmf figure 3-26 slicer level using peak detector for applications requiring fast attack and slow release from the threshold value it is reasonable to use the peak detectors. the threshold value is generated by an internal voltage divider. the release time is defined by the internal resistance values and the external capacitors. pkd_timing.wmf figure 3-27 peak detector timing p pospkd c k ? ? = 100 n negpkd c k ? ? = 100 [3 ? 33] [3 ? 32] signal t threshold slc(pin14) pos. peak detector (pin13) neg. peak detector (pin12) pospkd negpkd signal tda5250 d2 version 1.7 application data sheet 67 2007-02-26 component calculation: (rule of thumb) t l1 ? longest period of no signal change (low signal) t l2 ? longest period of no signal change (high signal) 3.6.3 peak detector - analog output signal the tda5250 data output can be digital (pin 28) or in analog form by using the peak detector output and changing some settings. to get an analog data output the slicer must be set to lowpass mode (reg. 0, d15 = lp = 0) and the peak detector capacitor at pin 12 or 13 has to be changed to a resistor of about 47kohm. pkd_analog.wmf figure 3-28 peak detector as analog buffer (v=1) 3.6.4 peak detector ? power down mode for a safe and fast threshold value generation the peak detector is turned on by the sequencer circuit (see section 2.4.18 ) only after the entire receiving path is active. in the off state the output of the positive peak detector is tied down to gnd and the output of the negative peak detector is pulled up to vcc. [3 ? 34] ? ? 100k l1 t 2 p c ? ? 100k l2 t 2 c n [3 ? 35] tda5250 d2 version 1.7 application data sheet 68 2007-02-26 pkd_pwdn.wmff figure 3-29 peak detector - power down mode pkd_pwdn3.wmf figure 3-30 power down mode 3.7 data valid detection in order to detect valid data two criteria must be fulfilled. one criteria is the data rate, which can be set in register 06h and 07h. the other one is the received rf power level, which can be set in register 08h in form of the rssi threshold voltage. thus for using the data valid detection fsk modulation is recommended. neg. peak detector (pin12) signal t threshold (pin14) pos. peak detector (pin13) power on power down vcc 0 peak detector power on data signal power on 2,2ms tda5250 d2 version 1.7 application data sheet 69 2007-02-26 timing for data detection looks like the following. two settings are possible: ?continuous? and ?single shot?, which can be set by d5 and d6 in register 00h. frequ_detect_timing_continuous.wmf figure 3-31 frequency detection timing in continuous mode note 1: chip internal signal ?sequencer enables data detection? has a low to high transition about 2.6ms after rx is activated (see figure 2-15 ). note 2: the positive edge of the ?window count complete? signal latches the result of comparison of the analog to digital converted rssi voltage with th3 (register 08h). a logic combination of this output and the result of the comparison with single/double th x defines the internal signal ?data_valid?. figure 3-31 shows that the logic is ready for the next conversion after 3 periods of the data signal. timing in single shot mode can be seen in the subsequent figure: frequ_detect_timing_singleshot_wmf figure 3-32 frequency detection timing in single shot mode data sequenzer enables data detection counter reset gate time compare with single th and latch result compare with double th and latch result (frequency) window count complete t t t t t t t start of conversion possible start of next conversion reset reset count count comp. comp. comp. ready* data sequenzer enables data detection counter reset gate time compare with single th and latch result compare with double th and latch result (frequency) window count complete t t t t t t t start of conversion no possible start of next conversion because of single shot mode reset count comp. comp. ready* tda5250 d2 version 1.7 application data sheet 70 2007-02-26 3.7.1 frequency window for data rate detection the high time of data is used to measure the frequency of the data signal. for manchester coding either the data frequency or half of the data frequency have to be detected corresponding to one high time or twice the high time of data signal. a time period of 3*2*t is necessary to decide about valid or invalid data. window_count_timing.wmf figure 3-33 window counter timing example to calculate the thresholds for a given data rate: - data signal manchester coded - data rate: 2kbit//s - f clk = 18,0896 mhz then the period equals to respectively the high time is 0,25ms. we set the thresholds to +-10% and get: t1= 0,225ms and t2= 0,275ms the thresholds th1 and th2 are calculated with following formulas t 0010 t2*t data possible gate 1 possible gate 2 01 t1 2*t1 t2 2*t2 0 t t 0,5ms 2kbit/s 1 t 2 = = ? [3 ? 36] 4 f t1 th1 clk ? = [3 ? 37] 4 f t2 th2 clk ? = [3 ? 38] tda5250 d2 version 1.7 application data sheet 71 2007-02-26 this yields the following results: th1~ 1017= 001111111001 b th2~ 1243= 010011011011 b which have to be programmed into the d0 to d11 bits of the count_th1 and count_th2 registers (subaddresses 06h and 07h), respectively. default values (window counter inactive): th1= 000000000000 b th2= 000000000001 b note: the timing window of +-10% of a given high time t in general does not correspond to a frequency window +-10% of the calculated data frequency. 3.7.2 rssi threshold voltage - rf input power the rf input power level is corresponding to a certain rssi voltage, which can be seen in section 3.5. the threshold th3 of this rssi voltage can be calculated with the following formula: as an example a desired rssi threshold voltage of 500mv results in th3~26=011010 b , which has to be written into d0 to d5 of the rssi_th3 register (sub address 08h). default value (rssi detection inactive): th3=111111 b 3.8 calculation of on_time and off_time on= (2 16 -1)-(f rc *t on ) off=( 2 16 -1)-(f rc *t off ) f rc = frequency of internal rc oszillator example: t on = 0,005s, t off = 0,055s, f rc = 32300hz on= 65535-(32300*0,005) ~ 65373= 1111111101011101 b off= 65535-(32300*0,055) ~ 63758= 1111100100001110 b the values have to be written into the d0 to d15 bits of the on_time and off_time registers (subaddresses 04h and 05h). ) 1 2 ( 6 ? ? = 1.2v th3 voltage threshold rssi desired [3 ? 39] [3 ? 40] [3 ? 41] tda5250 d2 version 1.7 application data sheet 72 2007-02-26 default values: on= 65215 = 1111111011000000 b off= 62335 = 1111001110000000 b t on ~10ms @ f rc = 32khz t off ~100ms @ f rc = 32khz 3.9 example for self polling mode the settings for self polling mode depend very much on the timing of the transmitted signal. to create an example we consider following data structure transmitted in fsk. data_timing011.wmf figure 3-34 example for transmitted data-structure according to existing synchronization techniques there are some synchronization bursts in front of the data added (code violation!). a minimum of 4 frames is transmitted. data are preferably manchester encoded to get fastest respond out of the data rate detection. target application: - received signal has code violation as described before - total mean current consumption below 1ma - data reception within max. 400ms after first transmitted frame one possible solution: t on = 15ms, t off = 135ms preamble t [ms] syncronisation preamble t [ms] data data data data 50ms 50ms 400ms data t [ms] 4 frames frame- details sync tda5250 d2 version 1.7 application data sheet 73 2007-02-26 this gives 15ms on time of a total period of 150ms which results in max. 0.9ma mean current consumption in self polling mode. the resulting worst case timing is shown in the following figure: data_timing021.wmf figure 3-35 3 possible timings description: assumption: the on time comes right after the first frame (case a). if off time is 135ms the receiver turns on during sync-pulses and the pwddd - pulse wakes up the p. if the on time is in the center of the 50ms gap of transmission (case b), the data detect logic will wake up the p 135ms later. if on time is over just before sync-pulses (case c), next on time is during data transmission and data detect logic will trigger a pwddd - pulse to wake up the p. note: in this example it is recommended to use the peak detector for slicer threshold generation, because of its fast attack and slow release characteristic. to overcome the data zero gap of 50ms larger external capacitors than noted in section 4.4 at pin12 and 13 are recommended. further information on calculating these components can be taken from section 3.6.2 . 3.10 sensitivity measurements 3.10.1 test setup the test setup used for the measurements is shown in the following figure. in case of ask modulation the rohde & schwarz smiq generator, which is a vector signal generator, is connected to the i/q modulation source amiq. this "baseband signal generator" is in turn controlled by the pc t [ms] data data data data 50ms 135ms 15ms p enables receiver until data completed interrupt due pwddd case a: t [ms] data data data data 50ms case b: 135ms 15ms p enables receiver until data completed interrupt due pwddd t [ms] data data data data 50ms case c: 135ms 15ms p enables receiver until data completed interrupt due pwddd ... receiver enabled tda5250 d2 version 1.7 application data sheet 74 2007-02-26 based software winqsim via a gpib interface. the amiq generator has a pseudo random binary sequence (prbs) generator and a bit error test set built in. the resulting i/q signals are applied to the smiq to generate a ask (ook) spectrum at the desired rf frequency. data is demodulated by the tda5250 and then sent back to the amiq to be compared with the originally sent data. the bit error rate is calculated by the bit error rate equipment inside the amiq. baseband coding in the form of manchester is applied to the i signal as can be seen in the subsequent figure. testsetup.wmf figure 3-36 ber test setup in the following figures the rf power level shown is the average power level. these investigations have been made on an infineon evaluation board using a data rate of 4 kbit/ s with manchester encoding and a data filter bandwidth of 7 khz. this is the standard configuration of our evaluation boards. all these measurements have been performed with several evaluation boards, so that production scattering and component tolerances are already included in these results. regarding the data filter bandwidth it has to be mentioned that a data rate of 4 kbit/s using manchester encoding results in a data frequency of 2 khz to 4 khz depending on the occurring data pattern. the test pattern given by the amiq is a pseudo random binary sequency (prbs9) with a 9 bit shift register. this pattern varies the resulting data frequency up to 4 khz. personal computer software winiqsim marker output rohde & schwarz i/q modulation source amiq amiq bert (bit error rate test set) i q rohde & schwarz vector signal generator smiq 03 ask / fsk rf signal manchester decoder dataout rfin dut transceiver testboard tda5250 clock data manchester encoder gpib / rs 232 tda5250 d2 version 1.7 application data sheet 75 2007-02-26 the best sensitivity performance can be achieved using a data filter bandwidth of 1.25 times the maximum occuring data frequency. the iq filter setting is depending on the modulation type. ask needs an iq filter of 50khz, 50khz deviation at fsk recommend a 100khz iq filter and 100khz deviation were measured with a 150khz iq filter a very practicable configuration is to set the chip-internal adjustable iq filter to the sum of fsk peak deviation and maximum datafrequency. concerning these aspects the bandwidth should be chosen small enough. with respect to both, the crystal tolerances and the tolerances of the crystal oscillator circuit of receiver and transmitter as well, a too small iq filter bandwidth will reduce the sensitivity again. so a compromise has to be made. for further details on chip tolerances see also section 3.2.7 3.10.2 sensitivity depending on the ambient temperature demonstrating a wide band of application possibilities the temperature behavior must not be forgotten. in automotive systems the required temperature range is from -40 c to +85 c. the receivers very good performance is documented in the following graph. the selected supply voltage is 5v, the influence of the supply voltage can be seen in the following section 3.10.3 the iq filter setting can be taken from the legend of figure 3-37 . ber_temp_5v.wmf figure 3-37 temperature behaviour figure 3-37 shows that ask as well as fsk sensitivity is in the range of -110 to -111dbm at 20c ambient temperature for a ber of 2e-3. notice that the sensitivity variation in this temperature range of -40 c to +85 c is only about 1.5 to 2 db. tda5250 d2 version 1.7 application data sheet 76 2007-02-26 3.10.3 ber performance depending on supply voltage due to the wide supply voltage range of this transeiver chip also the sensitivity behaviour over this parameter is documented is the subsequent graph. ber_vcc_20c..wmf figure 3-38 ber supply voltage please notice the tiny sensitivity changes of 1.5 to 2.5db, when variing the supply voltage. 3.10.4 datarates and sensitivity the tda 5250 can handle datarates up to 64kbit/s, as can be taken from the following figure. ( see section 4.1.4 ) tda5250 d2 version 1.7 application data sheet 77 2007-02-26 ber_datarate.wmf figure 3-39 datarates and sensitivity 3.10.5 sensitivity at frequency offset applying the test setup in figure 3-36 even a wide offset in the received frequency spectrum results only in a slight decrease of receiving sensitivity. at an offset of 100khz one of the two 50khz fsk peaks is at the 3db border of the iq filter (150khz), which is the reason for the decline of the sensitivity (see point a in figure 3-40 ). a frequency offset of 50khz (fsk deviation: 50khz) increases the data jitter of the demodulated signal and therefore results in little loss of sensitivity (see point b in figure 3-40 ). in this case one of the peaks of the fsk-spectrum lies in the dc-blocking notch of the baseband limiters. ber_frequoffset_fsk_3v..wmf figure 3-40 ber frequency offset tda5250 d2 version 1.7 application data sheet 78 2007-02-26 3.11 default setup default setup is hard wired on chip and effective after a reset or return of power supply. table 3-14 default setup parameter value ifx-board comment iq-filter bandwidth 150khz data filter bandwidth 7khz limiter lower fg 470hz 47nf slicing level generation rc 10nf nom. frequency capacity intern (ask tx, fsk rx) 4.5pf 868.3mhz fsk+ frequency capacity intern (fsk+, ask rx) 2.5pf +50khz fsk- frequency capacity intern (fsk-) 1.5pf -50khz lna gain high power amplifier high +10dbm rssi accuracy settling time 2.6ms 2.2nf adc measurement rssi on-time 10ms off-time 100ms clock out rx poweron 1mhz clock out tx poweron 1mhz clock out rx powerdown - clock out tx powerdown - xtal modulation switch bipolar xtal modulation shaping off rx / tx - jumper ask/fsk - jumper pwddd pwdn jumper removed operating mode slave tda5250 d2 version 1.7 reference data sheet 79 2007-02-26 4 reference 4.1 electrical data 4.1.1 absolute maximum ratings 4.1.2 operating range within the operational range the ic operates as explained in the circuit description. warning the maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the ic will result. table 4-1 absolute maximum ratings # parameter symbol limit values unit remarks min max 1 supply voltage v s -0.3 5.8 v 2 junction temperature t j -40 +125 c 3 storage temperature t s -40 +150 c 4 thermal resistance r thja 114 k/w 5 esd integrity, all pins v esd-cdm -1.5 +1.5 kv cdm according eia/jesd22-c101 6 esd integrity, except pin 8, 9, 11, 15, 18, 23, 30 v esd-hbm -2.0 +2.0 kv hbm according eia/jesd22-a114-b (1.5k ? , 100pf) 7 esd integrity, of pin 8, 9, 11, 15, 18, 23, 30 v esd-hbm -500 +500 v hbm according eia/jesd22-a114-b (1.5k ? , 100pf) table 4-2 operating range # parameter symbol limit values unit test conditions l item min max 1 supply voltage v s 2.1 5.5 v 2 ambient temperature t a -40 85 c 3 receive frequency f rx 868 870 mhz 4 transmit frequency f tx 868 870 mhz tda5250 d2 version 1.7 reference data sheet 80 2007-02-26 4.1.3 ac/dc characteristics ac/dc characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. typical characteristics are the median of the production. table 4-3 ac/dc characteristics with t a = 25 c, v vcc = 2.1 ... 5.5 v # parameter symbol limit values unit test conditions l item min typ max receiver characteristics 1 supply current rx fsk i rx_fsk 9 ma 3v, fsk, default 2 supply current rx fsk i rx_fsk 9.5 ma 5v, fsk, default 3 supply current rx ask i rx_ask 8.6 ma 3v, ask, default 4 supply current rx ask i rx_ask 9.1 ma 5v, ask, default 5 sensitivity fsk 10 -3 ber rf sens -109 dbm fsk@50khz, 4kbit/s manch. data, default 7khz datafilter, 100khz iq filter 6 sensitivity ask 10 -3 ber rf sens -109 dbm ask, 4kbit/s manch. data, default setup 7khz datafilter, 50khz iq filter 7 power down current i pwdn_rx 5 na 5.5v, all power down 8 system setup time (1 st power on or reset) t syssu 48 12 ms 9 clock out setup time t clksu 0.5 ms stable clkdiv output signal 10 receiver setup time t rxsu 1.54 2.2 2.86 ms data out (valid or invalid) 11 data detection setup time t ddsu 1.82 2.6 3.38 ms begin of data detection 12 rssi stable time t rssi 1.82 2.6 3.38 ms rfin -100dbm see chapter 4.5 13 data valid time t data_valid 3.35 ms 4kbit/s manch. detected (valid) 14 input p 1db , high gain p 1db -48dbm dbm 3v, default, high gain 15 input p 1db , low gain p 1db_low -32dbm dbm 3v, default, low gain 16 selectivity v bl_1mhz 50 db f rf +/-1mhz, default, rf sens +3db 17 lo leakage p lo -98 dbm 1157.73mhz tda5250 d2 version 1.7 reference data sheet 81 2007-02-26 1: without pin diode current (rx/tx-switch) 130ua@2.1v; 310ua@3v; 720ua@5v table 4-3 ac/dc characteristics with t a = 25 c, v vcc = 2.1 ... 5.5 v # parameter symbol limit values unit test conditions l item min typ max transmitter characteristics 1 supply current tx, fsk i tx 9.4 ma 2.1v, high power 1 2 supply current tx, fsk i tx 11.9 ma 3v, high power 1 3 supply current tx, fsk i tx 14.6 ma 5v, high power 1 4 output power p out 6 dbm 2.1v, high power 5 output power p out 9 dbm 3v, high power 6 output power p out 13 dbm 5v, high power 7 supply current tx, fsk i tx 4.1 ma 2.1v, low power 1 8 supply current tx, fsk i tx 4.9 ma 3v, low power 1 9 supply current tx, fsk i tx 6.8 ma 5v, low power 1 10 output power p out_low -30 dbm 2.1v, low power 11 output power p out_low -22 dbm 3v, low power 12 output power p out_low -3 dbm 5v, low power 13 power down current i pwdn_tx 5 na 5.5v, all power down 14 clock out setup time t clksu 0.5 ms stable clkdiv output signal 15 transmitter setup time t txsu 0.77 1.1 1.43 ms pwdn-->pon or rx-->tx 16 spurious f rf +/-f clock p clock dbm 3v, 50ohm board, default (1mhz) 17 spurious f rf +/-f xtal p 1st -66 dbm 3v, 50ohm board 18 spurious 2nd harmonic p 2nd -40 dbm 3v, 50ohm board 19 spurious 3rd harmonic p 3rd -50 dbm 3v, 50ohm board tda5250 d2 version 1.7 reference data sheet 82 2007-02-26 table 4-4 ac/dc characteristics with t a = 25 c, v vcc = 2.1 ... 5.5 v # parameter symbol limit values unit test conditions l item min typ max general characteristics 1 power down current timer mode (standby) i pwdn_32k 9 ua 3v, 32khz clock on 2 power down current timer mode (standby) i pwdn_32k 11 ua 5v, 32khz clock on 3 power down current with xtal on i pwdn_xtl 750 ua 3v, config9=1 4 power down current with xtal on i pwdn_xtl 860 ua 5v, config9=1 5 32khz oscillator freq. f 32khz 24 32 40 khz 6 xtal startup time t xtal 0.5 ms ifx board with crystal q1 as specified in section 4.4 7 load capacitance c c0max 5 pf 8 serial resistance of the crystal r rmax 100 w 9 input inductance xout l osc 2.7 uh with pad on evaluation board 10 input inductance xout l osc 2.45 uh without pad on evalution board 11 fsk demodulator gain g fsk 2.4 mv/ khz 12 rssi@-120dbm u -120dbm 0.35 v default setup 13 rssi@-100dbm u -100dbm 0.55 v default setup 14 rssi@-70dbm u -70dbm 1 v default setup 15 rssi@-50dbm u -50dbm 1.2 v default setup 16 rssi gradient g rssi 14 mv/ db default setup 17 iq-filter bandwidth f 3db_iq 115 150 185 khz default setup 18 data filter bandwidth f 3db_lp 5.3 7 8.7 khz default setup 19 vcc-vtune rx, pin3 v cc-tune,rx 0.5 1 1.6 v f ref =18.08956mhz 20 vcc-vtune tx, pin3 v cc-tune,tx 0.5 1.1 1.6 v f ref =18.08956mhz tda5250 d2 version 1.7 reference data sheet 83 2007-02-26 4.1.4 digital characteristics i 2 c bus timing figure 4-1 i 2 c bus timing 3-wire bus timing figure 4-2 3-wire bus timing busclk bus data en t buf t hd. dat t hd.sta t high t f t low t r t su .dat t hd.sta t sp t su.s to t su. sta t su. enas da pulsed or mandatory low busmode = low t su. ena sda t su. enas da t hig h scl sda bus_ena t hd .da t t h igh t f t lo w t r t su .d at t sp t su .st a bus_mode = hi gh t su.sto t w hen tda5250 d2 version 1.7 reference data sheet 84 2007-02-26 table 4-5 digital characteristics with t a = 25 c, v vdd = 2.1 ... 5.5 v # parameter symbol limit values unit test conditions l item min typ max 1 data rate tx ask f tx.ask 10 25 kbaud prbs9, manch.@+10dbm 1 2 data rate tx ask f tx.ask 10 64 kbaud prbs9, manch.@-5dbm 1 3 data rate tx fsk f tx.fsk 10 40 kbaud prbs9, manch.@+10dbm @50khz dev. 1 4 data rate rx ask f rx.ask 10 64 kbaud prbs9, manch. 5 data rate rx fsk f rx . fsk 10 64 kbaud prbs9, manch.@100khz dev. 6 digital inputs high-level input voltage low-level input voltage v ih v il v dd -0.35 0 v dd 0.35 v v 7 rxtx pin 5 tx operation, int. controlled v ol 0.4 1.15 v v @v dd =3v isink=800ua isink=3ma 8 clkdiv pin 26 t rise (0.1*v dd to 0.9*v dd ) t fall (0.9*v dd to 0.1*v dd ) output high voltage output low voltage t r t f v oh v ol 35 30 v dd -0.4 0.4 ns ns v v @v dd =3v load 10pf load 10pf isource=350ua isink=400ua bus interface characteristics 9 pulse width of spikes which must be suppressed by the input filter t sp 0 50 ns v dd =5v 10 low level output voltage at busdata v ol 0.4 v 3ma sink current v dd =5v 11 slc clock frequency f slc 0 400 khz v dd =5v 12 bus free time between stop and start condition t buf 1.3 s only i 2 c mode v dd =5v 13 hold time (repeated) start condition. t ho.sta 0.6 s after this period, the first clock pulse is generated, only i 2 c table 4-5 digital characteristics with t a = 25 c, v vdd = 2.1 ... 5.5 v tda5250 d2 version 1.7 reference data sheet 85 2007-02-26 1: limited by transmission channel bandwidth and depending on transmit power level; etsi regulation en 300 220 fullfilled, see section 3.1 2: c b = capacitance of one bus line # parameter symbol limit values unit test conditions l item min typ max 14 low period of busclk clock t low 1.3 s v dd =5v 15 high period of busclk clock t high 0.6 s v dd =5v 16 setup time for a repeated start condition t su.sta 0.6 s only i 2 c mode 17 data hold time t hd.dat 0 ns v dd =5v 18 data setup time t su.dat 100 ns v dd =5v 19 rise, fall time of both busdata and busclk signals t r , t f 20+ 0.1c b 300 ns v dd =5v 2 20 setup time for stop condition t su.sto 0.6 s only i 2 c mode v dd =5v 21 capacitive load for each bus line c b 400 pf v dd =5v 22 setup time for busclk to en t su.scl en 0.6 s only 3-wire mode v dd =5v 23 h-pulsewidth (en) t when 0.6 s v dd =5v tda5250 d2 version 1.7 reference data sheet 86 2007-02-26 4.2 test circuit the device performance parameters marked with in section 4.1.3 were measured on an infineon evaluation board (ifx board). tda5250_v42.schematic.pdf figure 4-3 schematic of the evaluation board tda5250 d2 version 1.7 reference data sheet 87 2007-02-26 4.3 test board layout gerberfiles for this testboard are available on request. tda5250_v42_layout.pdf figure 4-4 layout of the evaluation board note 1: the lna and pa matching network was designed for minimum required space and maximum performance and thus via holes were deliberately placed into solder pads. in case of reproduction please bear in mind that this may not be suitable for all automatic soldering processes. note 2: please keep in mind not to layout the clkdiv line directly in the neighborhood of the crystal and the associated components. tda5250 d2 version 1.7 reference data sheet 88 2007-02-26 4.4 bill of materials table 4-6 bill of materials reference value specification tolerance r1 4k7 0603 +/-5% r2 10 ? 0603 +/-5% r3 --- 0603 +/-5% r4 1m 0603 +/-5% r5 4k7 0603 +/-5% r6 4k7 0603 +/-5% r7 4k7 0603 +/-5% r8 6k8 0603 +/-5% r9 180 0603 +/-5% r10 180 0603 +/-5% r11 270 0603 +/-5% r12 15k 0603 +/-5% r13 10k 0603 +/-5% r14 180 0603 +/-5% r15 180 0603 +/-5% r16 1m 0603 +/-5% r17 1m 0603 +/-5% r18 1m 0603 +/-5% r19 560 0603 +/-5% r20 1k 0603 +/-5% r21 10 0603 +/-5% r22 00603 +/-5% r23 10 0603 +/-5% r24 180 0603 +/-5% c1 22pf 0603 +/-1% c2 1pf 0603 +/-0,1pf c3 5,6pf 0603 +/-0,1pf c4 2,2pf 0603 +/-0,1pf c5 1nf 0603 +/-5% c6 1nf 0603 +/-5% c7 15pf 0603 +/-1% c8 --- 0603 +/-0,1pf c9 47pf 0603 +/-1% c10 22pf 0603 +/-1% c11 --- 0603 +/-5% c12 10nf 0603 +/-10% c13 10nf 0603 +/-10% tda5250 d2 version 1.7 reference data sheet 89 2007-02-26 table 4-6 bill of materials reference value specification tolerance c14 10nf 0603 +/-10% c15 4.7pf 0603 +/-0,1pf c16 1.8pf 0603 +/-0,1pf c17 12pf 0603 +/-1% c18 10nf 0603 +/-10% c19 2,2nf 0603 +/-10% c20 47nf 0603 +/-10% c21 47nf 0603 +/-10% c22 47nf 0603 +/-10% c23 47nf 0603 +/-10% c24 100nf 0603 +/-10% c25 100nf 0603 +/-10% c26 --- 0603 +/-10% c27 100nf 0603 +/-10% c28 100nf 0603 +/-10% c29 100nf 0603 +/-10% c30 --- 0603 +/-10% l1 68nh simid 0603-c (epcos) +/-2% l2 12nh simid 0603-c (epcos) +/-2% l3 8.2nh simid 0603-c (epcos) +/-0.2nh ic1 tda5250 d2 ptssop38 ic2 ilq74 ic3 sfh6186 q1 18.08958mhz telcona: c0=2,1pf c1=8ff, c l =12pf s1 1-pol. t1 bc847b sot-23 (infineon) d1, d2 bar63-02w scd-80 (infineon) x1, x2 sma-socket x5 subd 25p. tda5250 d2 version 1.7 data sheet 90 2007-02-26 list of tables table 2-1 pin definition and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 12 table 2-2 sub address 00h: config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 19 table 2-3 sub address 00h: config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 19 table 2-4 sub address 00h: config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 22 table 2-5 pwddd pin operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 23 table 2-6 bus interface format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 24 table 2-7 chip address organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 25 table 2-8 i2c bus write mode 8 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 26 table 2-9 i2c bus write mode 16 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 26 table 2-10 i2c bus read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 26 table 2-11 3-wire bus write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 27 table 2-12 3-wire bus read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 27 table 2-13 sub addresses of data registers write. . . . . . . . . . . . . . . . . . . . . . page 28 table 2-14 sub addresses of data registers read. . . . . . . . . . . . . . . . . . . . . . page 28 table 2-15 sub address 00h: config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 28 table 2-16 sub addresses of data registers write. . . . . . . . . . . . . . . . . . . . . . page 29 table 2-17 sub addresses of data registers read. . . . . . . . . . . . . . . . . . . . . . page 29 table 2-18 sub address 00h: config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 29 table 2-19 sub address 01h: fsk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 30 table 2-20 sub address 02h: xtal_tuning . . . . . . . . . . . . . . . . . . . . . . . . . . page 30 table 2-21 sub address 03h: lpf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 30 table 2-22 sub addresses 04h / 05h: on/off_time . . . . . . . . . . . . . . . . . . . page 30 table 2-23 sub address 06h: count_th1 . . . . . . . . . . . . . . . . . . . . . . . . . . . page 30 table 2-24 sub address 07h: count_th2 . . . . . . . . . . . . . . . . . . . . . . . . . . . page 30 table 2-25 sub address 08h: rssi_th3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 31 table 2-26 sub address 0dh: clk_div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 31 table 2-27 sub address 0eh: xtal_config . . . . . . . . . . . . . . . . . . . . . . . . . page 31 table 2-28 sub address 0fh: block_pd . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 31 table 2-29 sub address 80h: status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 31 table 2-30 sub address 81h: adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 31 table 2-31 mode settings: config register . . . . . . . . . . . . . . . . . . . . . . . . . . page 32 table 2-32 clk_div output selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 37 table 2-33 clk_div setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 37 table 2-34 source for 6bit-adc selection (register 08h). . . . . . . . . . . . . . . . . page 37 table 3-1 crystal and crystal oscilator dependency . . . . . . . . . . . . . . . . . . . . . page 51 table 3-2 typical values of parasitic capacitances . . . . . . . . . . . . . . . . . . . . . . page 56 table 3-3 sub address 0eh: xtal_config. . . . . . . . . . . . . . . . . . . . . . . . . . page 58 table 3-4 sub address 02h: xtal_tuning . . . . . . . . . . . . . . . . . . . . . . . . . . page 58 table 3-5 sub address 01h: fsk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 58 table 3-6 default oscillator settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 59 table 3-7 internal tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 59 table 3-8 default setup (without internal tuning & without pin21 usage) . . . . . page 59 table 3-9 3db cutoff frequencies i/q filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 60 tda5250 d2 version 1.7 data sheet 91 2007-02-26 list of tables table 3-10 3db cutoff frequencies data filter . . . . . . . . . . . . . . . . . . . . . . . . . . page 62 table 3-11 limiter bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 63 table 3-12 sub address 00h: config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 64 table 3-13 sub address 00h: config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 65 table 3-14 default setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 78 table 4-1 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 79 table 4-2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 79 table 4-3 ac/dc characteristics with ta = 25 c, vvcc = 2.1 ... 5.5 v . . . . . page 80 table 4-4 ac/dc characteristics with ta = 25 c, vvcc = 2.1 ... 5.5 v . . . . . page 82 table 4-5 digital characteristics with ta = 25 c, vvdd = 2.1 ... 5.5 v . . . . . . page 84 table 4-6 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 88 tda5250 d2 version 1.7 data sheet 92 2007-02-26 list of figures figure 1-1 pg-tssop-38 package outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . page 10 figure 2-1 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 11 figure 2-2 main block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 18 figure 2-3 one i/q filter stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 20 figure 2-4 quadricorrelator demodulation characteristic . . . . . . . . . . . . . . . . . page 21 figure 2-5 data filter architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 22 figure 2-6 timing and data control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 23 figure 2-7 bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 24 figure 2-8 sub addresses overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 27 figure 2-9 wakeup logic states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 32 figure 2-10 timing for self polling mode (adc & data detect in one shot mode) page 32 figure 2-11 timing for timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 33 figure 2-12 frequency and rssi window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 33 figure 2-13 data valid circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 34 figure 2-14 data input/output circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 34 figure 2-15 1 st start or reset in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 35 figure 2-16 1st start or reset in pd mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 35 figure 2-17 sequencer?s capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 36 figure 2-18 clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 36 figure 3-1 rx/tx switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 39 figure 3-2 rx-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 40 figure 3-3 s11 measured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 41 figure 3-4 tx_mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 43 figure 3-5 tx_mode_simplified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 43 figure 3-6 equivalent power amplifier tank circuit . . . . . . . . . . . . . . . . . . . . . . . page 44 figure 3-7 output power p o (mw) and collector efficiency e vs. load resistor r l . page 45 figure 3-8 power output and collector current vs. frequency . . . . . . . . . . . . . . . page 46 figure 3-9 sparam_measured_200m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 47 figure 3-10 transmit spectrum 13.2ghz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 48 figure 3-11 transmit spectrum 300mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 48 figure 3-12 ask transmit spectrum 25kbaud, manch, prbs9, 9dbm, 3v . . . . page 49 figure 3-13 fsk transmit spectrum 40kbaud, manch, prbs9, 9dbm, 3v . . . . page 49 figure 3-14 crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 50 figure 3-15 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 52 figure 3-16 possible crystal oscillator frequencies . . . . . . . . . . . . . . . . . . . . . . . . page 53 figure 3-17 fsk modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 55 figure 3-18 fsk receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 55 figure 3-19 parasitics of the switching network . . . . . . . . . . . . . . . . . . . . . . . . . . page 56 figure 3-20 i/q filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 61 figure 3-21 iq filter and frequency characteristics of the receive system. . . . . . page 61 figure 3-22 limiter and pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 62 figure 3-23 limiter frequency characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . page 63 figure 3-24 typ. rssi level (eval board) @3v . . . . . . . . . . . . . . . . . . . . . . . . . page 64 tda5250 d2 version 1.7 data sheet 93 2007-02-26 list of figures figure 3-25 slicer level using rc integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 65 figure 3-26 slicer level using peak detector . . . . . . . . . . . . . . . . . . . . . . . . . . . page 66 figure 3-27 peak detector timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 66 figure 3-28 peak detector as analog buffer (v=1) . . . . . . . . . . . . . . . . . . . . . . . . page 67 figure 3-29 peak detector - power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . page 68 figure 3-30 power down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 68 figure 3-31 frequency detection timing in continuous mode . . . . . . . . . . . . . . . page 69 figure 3-32 frequency detection timing in single shot mode . . . . . . . . . . . . . . . page 69 figure 3-33 window counter timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 70 figure 3-34 example for transmitted data-structure. . . . . . . . . . . . . . . . . . . . . . . page 72 figure 3-35 3 possible timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 73 figure 3-36 ber test setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 74 figure 3-37 temperature behaviour. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 75 figure 3-38 ber supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 76 figure 3-39 datarates and sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 77 figure 3-40 ber frequency offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 77 figure 4-1 i2c bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 83 figure 4-2 3-wire bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 83 figure 4-3 schematic of the evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . page 86 figure 4-4 layout of the evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 87 data sheet 94 2007-02-26 index tda5250 d2 version 1.7 a absolute maximum ratings 79 ac/dc characteristics 80 application 10, 39 e electrical data 79 f features 9 functional block description 19 functional block diagram 18 functional description 11 o operating range 79 overview 9 p package outlines 10 pin configuration 11 pin definitions and functions 12 product description 9 r reference 79 s standards 83 |
Price & Availability of TDA5250D207
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